YosysHQ / yosys-benchLinks
Benchmarks for Yosys development
☆24Updated 5 years ago
Alternatives and similar repositories for yosys-bench
Users that are interested in yosys-bench are comparing it to the libraries listed below
Sorting:
- A padring generator for ASICs☆25Updated 2 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆50Updated 9 years ago
- Xilinx Unisim Library in Verilog☆85Updated 5 years ago
- Collection of test cases for Yosys☆18Updated 3 years ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆33Updated last year
- A Verilog Synthesis Regression Test☆37Updated last year
- Open source fpga project leveraging vtr CAD flow.☆26Updated 2 years ago
- ☆33Updated 2 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆84Updated last year
- An automatic clock gating utility☆50Updated 5 months ago
- ☆56Updated 3 years ago
- An open source PDK using TIGFET 10nm devices.☆50Updated 2 years ago
- Python interface to FPGA interchange format☆41Updated 2 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- ☆38Updated 3 years ago
- A library and command-line tool for querying a Verilog netlist.☆28Updated 3 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆42Updated 2 years ago
- Builds, flow and designs for the alpha release☆54Updated 5 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 4 years ago
- Source codes and calibration scripts for clock tree synthesis☆40Updated 5 years ago
- ☆23Updated 4 months ago
- mantle library☆44Updated 2 years ago
- Demo SoC for SiliconCompiler.☆60Updated last week
- Mutation Cover with Yosys (MCY)☆87Updated last week
- Bitstream relocation and manipulation tool.☆47Updated 2 years ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆91Updated 6 years ago
- Next-Generation FPGA Place-and-Route☆10Updated 7 years ago
- Gate-level visualization generator for SKY130-based chip designs.☆21Updated 4 years ago
- ☆15Updated 5 years ago
- Virtual development board for HDL design☆42Updated 2 years ago