NVlabs / iccad2020-GPUgatesimLinks
☆14Updated 4 years ago
Alternatives and similar repositories for iccad2020-GPUgatesim
Users that are interested in iccad2020-GPUgatesim are comparing it to the libraries listed below
Sorting:
- ILP SAT Detailed Router☆11Updated 5 years ago
- GL0AM GPU Accelerated Gate Level Logic Simulator☆22Updated last month
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆22Updated last week
- ☆33Updated 5 years ago
- HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration☆15Updated 4 years ago
- Fast Floating Point Operators for High Level Synthesis☆22Updated 2 years ago
- EDA wiki☆53Updated 2 years ago
- Stencil with Optimized Dataflow Architecture☆12Updated last year
- EDA physical synthesis optimization kit☆60Updated last year
- FPGA acceleration of arbitrary precision floating point computations.☆40Updated 3 years ago
- An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization☆31Updated last year
- An infrastructure for integrated EDA☆41Updated 2 years ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆33Updated 2 months ago
- A High-performance Timing Analysis Tool for VLSI Systems☆9Updated 4 years ago
- ☆13Updated 3 years ago
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Updated 7 years ago
- DATC Robust Design Flow.☆36Updated 5 years ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆113Updated last year
- DATuner Repository☆18Updated 6 years ago
- ☆44Updated 5 years ago
- An open multiple patterning framework☆78Updated last year
- ☆21Updated 2 years ago
- LLM Evaluation Framework for Hardware Design Using Python-Embedded DSLs☆16Updated 11 months ago
- DAC'22 paper: "Automated Accelerator Optimization Aided by Graph Neural Networks"☆40Updated last year
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated 11 months ago
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆29Updated 6 months ago
- GPU-based logic synthesis tool☆86Updated last month
- Differentiable Combinatorial Scheduling at Scale (ICML'24). Mingju Liu, Yingjie Li, Jiaqi Yin, Zhiru Zhang, Cunxi Yu.☆21Updated 9 months ago
- A stream to RTL compiler based on MLIR and CIRCT☆15Updated 2 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago