NVlabs / iccad2020-GPUgatesim
☆12Updated 4 years ago
Related projects ⓘ
Alternatives and complementary repositories for iccad2020-GPUgatesim
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated 2 months ago
- ILP SAT Detailed Router☆11Updated 4 years ago
- Stencil with Optimized Dataflow Architecture☆12Updated 8 months ago
- HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration☆15Updated 4 years ago
- Streaming Message Interface: High-Performance Distributed Memory Programming on Reconfigurable Hardware☆16Updated 2 years ago
- ☆21Updated 2 years ago
- Fast Floating Point Operators for High Level Synthesis☆19Updated last year
- EDA wiki☆50Updated last year
- ☆29Updated 4 years ago
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Updated 7 years ago
- DATuner Repository☆18Updated 6 years ago
- FPGA acceleration of arbitrary precision floating point computations.☆37Updated 2 years ago
- Provides the code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators" by Luk…☆17Updated 5 years ago
- ☆12Updated 2 years ago
- ☆28Updated 2 years ago
- [ICCAD 22]DeePEB: A neural network based PEB solver☆8Updated last year
- EDA physical synthesis optimization kit☆50Updated last year
- Global Router Built for ICCAD Contest 2019☆30Updated 4 years ago
- OpenDesign Flow Database☆16Updated 6 years ago
- AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…☆21Updated last month
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆31Updated 2 weeks ago
- ☆50Updated 3 weeks ago
- SForum 2020 : "A Run-time Hardware Routing Implementation for CGRA Overlays" code and data.☆11Updated 4 years ago
- ☆20Updated 6 months ago
- Convert C files into Verilog☆16Updated 5 years ago
- Datasets for EDA LLM research☆18Updated 5 months ago
- DATC Robust Design Flow.☆37Updated 4 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆19Updated this week
- Interconnect Prototyping Assistant (IPA) is an interconnect modeling and generation framework built atop [MatchLib] (https://github.com/N…☆13Updated 3 months ago
- Accelerator simulation framework using nn_dataflow traces and energy, etc. post-processing☆7Updated 5 years ago