NVlabs / iccad2020-GPUgatesimLinks
☆14Updated 5 years ago
Alternatives and similar repositories for iccad2020-GPUgatesim
Users that are interested in iccad2020-GPUgatesim are comparing it to the libraries listed below
Sorting:
- ILP SAT Detailed Router☆12Updated 5 years ago
- GL0AM GPU Accelerated Gate Level Logic Simulator☆28Updated 3 months ago
- ☆33Updated 5 years ago
- LLM Evaluation Framework for Hardware Design Using Python-Embedded DSLs☆17Updated last year
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆23Updated last week
- HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration☆15Updated 5 years ago
- EDA physical synthesis optimization kit☆62Updated 2 years ago
- EDA wiki☆53Updated 2 years ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆34Updated 5 months ago
- DATC Robust Design Flow.☆36Updated 5 years ago
- ☆13Updated 3 years ago
- DATuner Repository☆17Updated 7 years ago
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated last year
- OpenDesign Flow Database☆16Updated 7 years ago
- An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization☆32Updated 2 years ago
- ☆21Updated 3 years ago
- A polyhedral compiler for hardware accelerators☆59Updated last year
- A Generic Distributed Auto-Tuning Infrastructure☆22Updated 4 years ago
- Fast Floating Point Operators for High Level Synthesis☆21Updated 2 years ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆115Updated last year
- Stencil with Optimized Dataflow Architecture☆12Updated last year
- An infrastructure for integrated EDA☆42Updated 2 years ago
- ☆44Updated 5 years ago
- ☆77Updated 5 months ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Updated 8 years ago
- DAC'22 paper: "Automated Accelerator Optimization Aided by Graph Neural Networks"☆40Updated 2 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- A configurable SRAM generator☆57Updated 3 months ago
- Differentiable Combinatorial Scheduling at Scale (ICML'24). Mingju Liu, Yingjie Li, Jiaqi Yin, Zhiru Zhang, Cunxi Yu.☆20Updated last year