tarik-ibrahimovic / eduBOS5Links
A compact, configurable RISC-V core
☆12Updated 3 months ago
Alternatives and similar repositories for eduBOS5
Users that are interested in eduBOS5 are comparing it to the libraries listed below
Sorting:
- ☆43Updated 3 years ago
- SpiceBind – spice inside HDL simulator☆56Updated 4 months ago
- An open-source HDL register code generator fast enough to run in real time.☆76Updated 2 weeks ago
- The Open Source Hardware Accelerator for Efficient Neural Network Inference☆48Updated this week
- ☆27Updated 7 months ago
- This project contains Verilog designs and a PCB for the implementation of CSI-2 camera interface to HDMI bridge on a Gatemate FPGA from C…☆18Updated 3 months ago
- UART models for cocotb☆31Updated 2 months ago
- The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor☆15Updated 2 years ago
- Fixed-point library with bittrue implementations in VHDL (for FPGA) and python (for simulation)☆25Updated last year
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆67Updated 3 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆51Updated last year
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆41Updated last month
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆76Updated 3 months ago
- Python script to transform a VCD file to wavedrom format☆81Updated 3 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆38Updated 2 weeks ago
- submission repository for efabless mpw6 shuttle☆30Updated last year
- Drawio => VHDL and Verilog☆61Updated 2 years ago
- ☆32Updated last week
- Python Tool for UVM Testbench Generation☆54Updated last year
- UART -> AXI Bridge☆63Updated 4 years ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆63Updated last year
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆80Updated 3 years ago
- SystemVerilog RTL Linter for YoSys☆21Updated 11 months ago
- Limited python / cocotb interface to Xilinx/AMD Vivado simulator.☆66Updated last month
- Making cocotb testbenches that bit easier☆36Updated 2 weeks ago
- A simple DDR3 memory controller☆61Updated 2 years ago
- Open-source RHBD (Radiation Hardened by Design) Standard-Cell Library for SKY130☆10Updated 5 months ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- 55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd.☆91Updated this week