HDL-first mixed-signal co-simulation: embed ngspice circuits in Verilog through VPI
☆66Sep 14, 2026Updated this week
Alternatives and similar repositories for spicebind
Users that are interested in spicebind are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆39Sep 10, 2026Updated last week
- Making cocotb testbenches that bit easier☆42Feb 28, 2026Updated 6 months ago
- Apheleia Verification Library. A Python based HDL verification library sitting on top of cocotb☆60Updated this week
- RTLMeter benchmark suite☆33Updated this week
- Debug waveforms with GDB☆33Nov 12, 2025Updated 10 months ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Custom IC Design Platform☆123Updated this week
- Characterizer☆39Aug 26, 2026Updated 3 weeks ago
- Open-source RTL logic simulator with GPU acceleration (Metal, CUDA, HIP/AMD)☆85Aug 10, 2026Updated last month
- Netlist API (and more) for EDA flow development☆162Updated this week
- This project contains Verilog designs and a PCB for the implementation of CSI-2 camera interface to HDMI bridge on a Gatemate FPGA from C…☆21Jul 28, 2025Updated last year
- Custom IC Creator Simulation tools☆27Aug 14, 2026Updated last month
- LunaPnR is a place and router for integrated circuits☆47Feb 11, 2026Updated 7 months ago
- Fabric generator and CAD tools graphical frontend☆19Aug 5, 2025Updated last year
- SystemVerilog design elaborator into word-level netlist form☆250Updated this week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A Formal Verification Methodology to lower the adoption barriers for Formal Verification of ASIC and FPGA designs in the Space sector (th…☆25Jun 29, 2026Updated 2 months ago
- Open-source PDK version manager☆65Updated this week
- ☆162Aug 19, 2026Updated last month
- A novel Design-for-Test flow using LibreLane☆46May 9, 2026Updated 4 months ago
- Digital logic benchmark suite☆87Sep 10, 2026Updated last week
- Hardware Description Library☆96Feb 17, 2026Updated 7 months ago
- Open source RTL simulation acceleration on commodity hardware☆36Apr 13, 2023Updated 3 years ago
- Analog Circuit Simulator☆25Sep 6, 2024Updated 2 years ago
- Examples of analog circuit design with sEKV for the open source IHP 130nm technology☆32Jun 5, 2025Updated last year
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Open Agentic Design Automation - The open agent interface for EDA: Agent–EDA Contract☆26Aug 12, 2026Updated last month
- A Python to VHDL compiler☆17Apr 28, 2025Updated last year
- HeiChips 2025 LibreLane Workshop☆18Aug 25, 2025Updated last year
- Greyhound on IHP SG13G2 0.13 μm BiCMOS process☆110Aug 31, 2026Updated 2 weeks ago
- Elements Software Development Kit☆13Jan 8, 2026Updated 8 months ago
- Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments, allowing host compiled programs to run in a log…☆79Feb 12, 2026Updated 7 months ago
- Development repository for openEMS workflow for IHP SG13G2☆69Sep 12, 2026Updated last week
- Custom IC Creator (ciccreator) is a compiler that takes in a object definition file (JSON), a SPICE file, and a design rule file and outp…☆45Aug 8, 2026Updated last month
- An opinionated build environment for EDA projects☆19Jul 20, 2025Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- wafer.space GF180MCU Run 1☆41Apr 27, 2026Updated 4 months ago
- Connect to your VHDL simulation via JTAG! GDB <-TCP-> OpenOCD <-remote bitbang-> cosim_jtag <-VHPI or FLI-> VHDL simulator.☆15Dec 30, 2025Updated 8 months ago
- SystemVerilog file list pruner☆19Updated this week
- ☆42Updated this week
- RFIC EM simulation: Create AWS Palace model from GDSII layout files☆68Updated this week
- Digital Design Equivalence Checking☆109Updated this week
- CIRCT and Yosys interoperability, demonstrated with CHISEL☆18Feb 3, 2026Updated 7 months ago