Alternatives and similar repositories for spicebind

Users that are interested in spicebind are comparing it to the libraries listed below

• Intuity / forastero
  Making cocotb testbenches that bit easier
  ☆36Updated 3 weeks ago
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆31Updated 6 months ago
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆76Updated 3 weeks ago
• schang412 / cocotbext-spi
  ☆27Updated 7 months ago
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 9 months ago
• christoph-weiser / mpw6
  submission repository for efabless mpw6 shuttle
  ☆30Updated last year
• snishizawa / libretto
  Characterizer
  ☆30Updated 3 months ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆76Updated 3 months ago
• VHDL / PoC
  IP Core Library - Published and maintained by the Open Source VHDL Group
  ☆40Updated last month
• heyfey / sv-pathfinder
  VS Code extension for SystemVerilog design navigation and RTL tracing. Seamlessly integrates with waveform viewer for post-simulation deb…
  ☆29Updated last week
• pulp-platform / artistic
  An Open-Source Toolchain for Top-Metal IC Art and Ultra-High-Fidelity GDSII Renders
  ☆19Updated 3 months ago
• fvutils / pyhdl-if
  Python interface for cross-calling with HDL
  ☆41Updated this week
• pulp-platform / svase
  ☆33Updated 10 months ago
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆67Updated last month
• openecos-projects / icsprout55-pdk
  55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd.
  ☆114Updated this week
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆81Updated 3 years ago
• iic-jku / SKY130_SAR-ADC1
  Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license
  ☆48Updated 8 months ago
• umarcor / osvb
  Open Source Verification Bundle for VHDL and System Verilog
  ☆48Updated last year
• wallento / cocotbext-wishbone
  ☆18Updated 11 months ago
• VHDL / Interfaces
  Interface definitions for VHDL-2019.
  ☆28Updated 3 months ago
• fransschreuder / xpm_vhdl
  A translation of the Xilinx XPM library to VHDL for simulation purposes
  ☆57Updated last week
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆39Updated last week
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆42Updated last year
• fossi-foundation / ciel
  Open-source PDK version manager
  ☆30Updated last month
• vsdip / vsdsram_sky130
  ☆43Updated 3 years ago
• antmicro / verilator-verification
  Test dashboard for verification features in Verilator
  ☆28Updated this week
• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆51Updated this week
• tarik-ibrahimovic / eduBOS5
  A compact, configurable RISC-V core
  ☆12Updated 3 months ago
• AsFigo / svck
  ☆14Updated 5 months ago
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆57Updated 2 months ago