Alternatives and similar repositories for spicebind

Users that are interested in spicebind are comparing it to the libraries listed below

• Intuity / forastero
  Making cocotb testbenches that bit easier
  ☆34Updated 3 weeks ago
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆72Updated last month
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 6 months ago
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆31Updated 3 months ago
• schang412 / cocotbext-spi
  ☆23Updated 3 months ago
• christoph-weiser / mpw6
  submission repository for efabless mpw6 shuttle
  ☆30Updated last year
• VHDL / PoC
  IP Core Library - Published and maintained by the Open Source VHDL Group
  ☆21Updated last month
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆73Updated 2 weeks ago
• fransschreuder / xpm_vhdl
  A translation of the Xilinx XPM library to VHDL for simulation purposes
  ☆55Updated 3 weeks ago
• pulp-platform / artistic
  An Open-Source Toolchain for Top-Metal IC Art and Ultra-High-Fidelity GDSII Renders
  ☆18Updated 2 weeks ago
• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆48Updated this week
• wallento / cocotbext-wishbone
  ☆14Updated 7 months ago
• snishizawa / libretto
  Characterizer
  ☆29Updated 2 months ago
• umarcor / osvb
  Open Source Verification Bundle for VHDL and System Verilog
  ☆45Updated last year
• stineje / sky130RHBDlib
  Open-source RHBD (Radiation Hardened by Design) Standard-Cell Library for SKY130
  ☆8Updated 2 months ago
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆71Updated 3 weeks ago
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆44Updated 6 months ago
• alexforencich / cocotbext-uart
  UART models for cocotb
  ☆29Updated 2 years ago
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆56Updated last month
• MJoergen / formal
  Playing around with Formal Verification of Verilog and VHDL
  ☆61Updated 4 years ago
• StefanSchippers / xschem_sky130
  XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.
  ☆64Updated last month
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆78Updated 2 years ago
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆53Updated last year
• VHDL / Interfaces
  Interface definitions for VHDL-2019.
  ☆26Updated last week
• pulp-platform / svase
  ☆32Updated 7 months ago
• fvutils / pyhdl-if
  Python interface for cross-calling with HDL
  ☆34Updated last week
• tarik-ibrahimovic / eduBOS5
  A compact, configurable RISC-V core
  ☆11Updated last week
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆42Updated last year
• bpadalino / vhdl-format
  VHDL String Formatting Library
  ☆25Updated last year
• fossi-foundation / ciel
  Open-source PDK version manager
  ☆19Updated last month