najaeda / najaView external linksLinks
Structural Netlist API (and more) for EDA post synthesis flow development
☆134Updated this week
Alternatives and similar repositories for naja
Users that are interested in naja are comparing it to the libraries listed below
Sorting:
- A standalone structural (gate-level) verilog parser☆40Feb 2, 2026Updated last week
- SystemVerilog frontend for Yosys☆196Feb 6, 2026Updated last week
- ☆99Updated this week
- Logic circuit analysis and optimization☆45Feb 2, 2026Updated last week
- Yosys plugin for logic locking and supply-chain security☆23Apr 5, 2025Updated 10 months ago
- Fully defined liberty (std. cells in VLSI) data structure, efficient parser & formatter☆23Feb 3, 2026Updated last week
- Interchange formats for chip design.☆36Feb 3, 2026Updated last week
- A Standalone Structural Verilog Parser☆99Mar 31, 2022Updated 3 years ago
- ☆20Jun 23, 2024Updated last year
- design and verification of asynchronous circuits☆43Jan 18, 2026Updated 3 weeks ago
- Fabric generator and CAD tools.☆217Updated this week
- GOMIL: Global Optimization of Multiplier by Integer Linear Programming☆13Aug 25, 2021Updated 4 years ago
- Python version of tools to work with AIG formatted files☆12May 20, 2025Updated 8 months ago
- An abstraction library for interfacing EDA tools☆750Updated this week
- SystemVerilog synthesis tool☆227Mar 10, 2025Updated 11 months ago
- Library of open source PDKs☆65Feb 3, 2026Updated last week
- Datasets for EDA LLM research☆38Jan 17, 2025Updated last year
- The next generation of OpenLane, rewritten from scratch with a modular architecture☆332Dec 2, 2025Updated 2 months ago
- ☆81Jan 5, 2026Updated last month
- Hardware Description Library☆88Jan 29, 2026Updated 2 weeks ago
- ☆59Jul 11, 2025Updated 7 months ago
- Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.☆101Jan 30, 2025Updated last year
- ☆35Feb 2, 2026Updated last week
- A repository for Known Good Designs (KGDs). Does not contain any design files with NDA-sensitive information.☆39Jun 10, 2021Updated 4 years ago
- SystemVerilog compiler and language services☆948Updated this week
- Coriolis VLSI EDA Tool (LIP6)☆78Jan 25, 2026Updated 2 weeks ago
- A library and command-line tool for querying a Verilog netlist.☆29Jun 13, 2022Updated 3 years ago
- ☆19Feb 2, 2026Updated last week
- Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation☆232Feb 6, 2026Updated last week
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆442Sep 6, 2025Updated 5 months ago
- Making cocotb testbenches that bit easier☆37Oct 26, 2025Updated 3 months ago
- Characterizer☆31Nov 19, 2025Updated 2 months ago
- An open-source EDA infrastructure and tools from netlist to GDS☆481Jan 10, 2026Updated last month
- A fork of Yosys that integrates the CellIFT pass☆13Jul 23, 2025Updated 6 months ago
- ☆14Feb 3, 2025Updated last year
- Python Verilog-AMS Parser☆12Oct 13, 2015Updated 10 years ago
- Synthesiser for Asynchronous Verilog Language☆20Oct 29, 2014Updated 11 years ago
- OpenROAD Agent. This repository contain the model to train and testing the model using EDA Corpus dataset.☆21Jul 24, 2025Updated 6 months ago
- Primitives for GF180MCU provided by GlobalFoundries.☆12Jul 6, 2025Updated 7 months ago