Structural Netlist API (and more) for EDA post synthesis flow development
☆135Feb 27, 2026Updated this week
Alternatives and similar repositories for naja
Users that are interested in naja are comparing it to the libraries listed below
Sorting:
- A standalone structural (gate-level) verilog parser☆40Feb 2, 2026Updated last month
- SystemVerilog frontend for Yosys☆202Feb 22, 2026Updated last week
- ☆102Updated this week
- Logic circuit analysis and optimization☆45Feb 2, 2026Updated last month
- Yosys plugin for logic locking and supply-chain security☆23Apr 5, 2025Updated 11 months ago
- Fully defined liberty (std. cells in VLSI) data structure, efficient parser & formatter☆23Feb 24, 2026Updated last week
- Interchange formats for chip design.☆37Feb 15, 2026Updated 2 weeks ago
- A Standalone Structural Verilog Parser☆99Mar 31, 2022Updated 3 years ago
- ☆22Jun 23, 2024Updated last year
- design and verification of asynchronous circuits☆43Updated this week
- An easy-to-use, silicon-proven (e)FPGA generator with an integrated CAD toolchain 🏗️☆218Feb 23, 2026Updated last week
- Python version of tools to work with AIG formatted files☆12May 20, 2025Updated 9 months ago
- GOMIL: Global Optimization of Multiplier by Integer Linear Programming☆13Aug 25, 2021Updated 4 years ago
- An abstraction library for interfacing EDA tools☆756Feb 18, 2026Updated 2 weeks ago
- SystemVerilog synthesis tool☆228Mar 10, 2025Updated 11 months ago
- Library of open source PDKs☆64Feb 3, 2026Updated last month
- Datasets for EDA LLM research☆38Jan 17, 2025Updated last year
- SpiceBind – spice inside HDL simulator☆56Jun 30, 2025Updated 8 months ago
- The next generation of OpenLane, rewritten from scratch with a modular architecture☆334Dec 2, 2025Updated 3 months ago
- ☆83Jan 5, 2026Updated 2 months ago
- Hardware Description Library☆87Feb 17, 2026Updated 2 weeks ago
- ☆59Jul 11, 2025Updated 7 months ago
- ☆36Feb 2, 2026Updated last month
- Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.☆101Jan 30, 2025Updated last year
- A repository for Known Good Designs (KGDs). Does not contain any design files with NDA-sensitive information.☆40Jun 10, 2021Updated 4 years ago
- SystemVerilog compiler and language services☆968Updated this week
- A library and command-line tool for querying a Verilog netlist.☆29Jun 13, 2022Updated 3 years ago
- Coriolis VLSI EDA Tool (LIP6)☆81Jan 25, 2026Updated last month
- ☆21Updated this week
- Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation☆233Feb 27, 2026Updated last week
- Greyhound on IHP SG13G2 0.13 μm BiCMOS process☆83Jan 28, 2026Updated last month
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆449Feb 23, 2026Updated last week
- Making cocotb testbenches that bit easier☆37Updated this week
- Characterizer☆31Nov 19, 2025Updated 3 months ago
- Synthesiser for Asynchronous Verilog Language☆20Oct 29, 2014Updated 11 years ago
- ☆14Feb 3, 2025Updated last year
- A fork of Yosys that integrates the CellIFT pass☆13Jul 23, 2025Updated 7 months ago
- LEC - Logic Equivalence Checking - Formal Verification☆33Updated this week
- OpenROAD Agent. This repository contain the model to train and testing the model using EDA Corpus dataset.☆21Jul 24, 2025Updated 7 months ago