najaeda / naja
Structural Netlist API (and more) for EDA post synthesis flow development
☆65Updated this week
Related projects ⓘ
Alternatives and complementary repositories for naja
- Plugins for Yosys developed as part of the F4PGA project.☆81Updated 5 months ago
- An automatic clock gating utility☆40Updated 3 months ago
- Qrouter detail router for digital ASIC designs☆56Updated last month
- Coriolis VLSI EDA Tool (LIP6)☆54Updated this week
- 👾 Design ∪ Hardware☆72Updated this week
- A SystemVerilog source file pickler.☆51Updated 3 weeks ago
- A library and command-line tool for querying a Verilog netlist.☆26Updated 2 years ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆109Updated last year
- ☆30Updated last year
- BAG framework☆41Updated 3 months ago
- Framework Open EDA Gui☆60Updated this week
- Hardware Description Library☆69Updated 2 months ago
- ☆29Updated 2 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆67Updated 6 months ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆39Updated last year
- Sphinx Extension which generates various types of diagrams from Verilog code.☆54Updated last year
- ☆39Updated 4 years ago
- IO and Pin Placer for Floorplan-Placement Subflow☆23Updated 4 years ago
- Open source process design kit for 28nm open process☆42Updated 6 months ago
- Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.☆94Updated this week
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆33Updated 4 years ago
- slang-based frontend for Yosys☆41Updated this week
- ☆36Updated 2 years ago
- Netgen complete LVS tool for comparing SPICE or verilog netlists☆109Updated 3 weeks ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆31Updated this week
- Builds, flow and designs for the alpha release☆53Updated 4 years ago
- UCSD Sizer for leakage/dynamic power recovery, timing recovery☆17Updated 5 years ago
- Benchmarks for Yosys development☆21Updated 4 years ago
- IRSIM switch-level simulator for digital circuits☆30Updated 6 months ago