Alternatives and similar repositories for naja

Users that are interested in naja are comparing it to the libraries listed below

• lip6 / coriolis
  Coriolis VLSI EDA Tool (LIP6)
  ☆69Updated 3 weeks ago
• librelane / librelane
  ASIC implementation flow infrastructure
  ☆80Updated last week
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated last year
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆50Updated 4 months ago
• stineje / CharLib
  Open-source repository for a standard-cell library characterizer using complete open-source tools
  ☆35Updated 3 weeks ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆151Updated last week
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆117Updated last year
• pulp-platform / svase
  ☆32Updated 7 months ago
• os-fpga / Raptor
  Raptor end-to-end FPGA Compiler and GUI
  ☆84Updated 8 months ago
• dan-fritchman / Hdl21
  Hardware Description Library
  ☆82Updated 4 months ago
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆102Updated last year
• siliconcompiler / lambdapdk
  Library of open source Process Design Kits (PDKs)
  ☆50Updated last week
• FPGA-Research / FABulous
  Fabric generator and CAD tools.
  ☆193Updated this week
• pulp-platform / cheshire-ihp130-o
  ☆49Updated 4 months ago
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆155Updated 2 months ago
• mineda-support / ICPS2023_5
  ☆55Updated last month
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆59Updated 10 months ago
• OpenTimer / Parser-Verilog
  A Standalone Structural Verilog Parser
  ☆97Updated 3 years ago
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆155Updated last month
• hdl / conda-eda
  Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.
  ☆101Updated 6 months ago
• parallaxsw / OpenSTA
  ☆81Updated last week
• efabless / mpw_precheck
  ☆42Updated 6 months ago
• woset-workshop / woset-workshop.github.io
  Workshop on Open-Source EDA Technology (WOSET)
  ☆48Updated 9 months ago
• RIOSLaboratory / OpenRPDK28
  Open source process design kit for 28nm open process
  ☆60Updated last year
• efabless / chipignite-resources
  ☆83Updated 2 years ago
• aolofsson / POSH
  ☆44Updated 5 years ago
• efabless / cace
  Circuit Automatic Characterization Engine
  ☆50Updated 6 months ago
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆208Updated 5 months ago
• SymbiFlow / sphinxcontrib-hdl-diagrams
  Sphinx Extension which generates various types of diagrams from Verilog code.
  ☆61Updated last year
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆46Updated 2 months ago