zeroasiccorp / switchboard
Communication framework for RTL simulation and emulation.
☆285Updated last month
Alternatives and similar repositories for switchboard
Users that are interested in switchboard are comparing it to the libraries listed below
Sorting:
- CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…☆370Updated this week
- Universal Memory Interface (UMI)☆145Updated last month
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆255Updated this week
- Bringup-Bench is a collection of standalone minimal library and system dependence benchmarks useful for bringing up newly designed CPUs, …☆176Updated 3 weeks ago
- CORE-V Family of RISC-V Cores☆265Updated 2 months ago
- This tool translates synthesizable SystemC code to synthesizable SystemVerilog.☆271Updated 2 weeks ago
- Fabric generator and CAD tools☆179Updated 3 weeks ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆86Updated 2 weeks ago
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆162Updated 3 months ago
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆223Updated last year
- Example designs showing different ways to use F4PGA toolchains.☆275Updated last year
- SystemVerilog synthesis tool☆190Updated 2 months ago
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆174Updated last week
- Self checking RISC-V directed tests☆105Updated 2 months ago
- A configurable RTL to bitstream FPGA toolchain☆33Updated last week
- RISC-V Verification Interface☆89Updated 2 months ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆133Updated last week
- FOSS Flow For FPGA☆386Updated 4 months ago
- The next generation of OpenLane, rewritten from scratch with a modular architecture☆284Updated 2 months ago
- VeeR EL2 Core☆275Updated 2 weeks ago
- A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …☆96Updated this week
- Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.☆324Updated 2 months ago
- Open source ISS and logic RISC-V 32 bit project☆52Updated 2 weeks ago
- A huge VHDL library for FPGA and digital ASIC development☆382Updated this week
- Standard Cell Library based Memory Compiler using FF/Latch cells☆145Updated 10 months ago
- Opensource DDR3 Controller☆322Updated 3 weeks ago
- Code generation tool for control and status registers☆381Updated 2 months ago
- Example LED blinking project for your FPGA dev board of choice☆175Updated 2 months ago
- An overview of TL-Verilog resources and projects☆78Updated last month
- Control and Status Register map generator for HDL projects☆116Updated this week