zeroasiccorp / switchboardLinks
Communication framework for RTL simulation and emulation.
☆308Updated this week
Alternatives and similar repositories for switchboard
Users that are interested in switchboard are comparing it to the libraries listed below
Sorting:
- Universal Memory Interface (UMI)☆157Updated last week
- CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…☆483Updated this week
- Fabric generator and CAD tools.☆215Updated last week
- Open-source RTL logic simulator with CUDA acceleration☆255Updated 4 months ago
- ASIC implementation flow infrastructure, successor to OpenLane☆276Updated this week
- Bringup-Bench is a collection of standalone minimal library and system dependence benchmarks useful for bringing up newly designed CPUs, …☆220Updated 3 months ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆317Updated this week
- Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.☆377Updated 11 months ago
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆195Updated last month
- eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V☆238Updated last week
- A hardware component library developed with ROHD.☆111Updated this week
- 10Gb Ethernet Switch☆252Updated 3 months ago
- Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.☆267Updated 3 years ago
- SystemVerilog synthesis tool☆227Updated 10 months ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆164Updated 2 months ago
- https://caravel-user-project.readthedocs.io☆228Updated 11 months ago
- Raptor end-to-end FPGA Compiler and GUI☆95Updated last year
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆127Updated 6 months ago
- SystemVerilog frontend for Yosys☆196Updated this week
- ☆375Updated 2 years ago
- A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …☆117Updated 6 months ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆201Updated this week
- The multi-core cluster of a PULP system.☆111Updated this week
- CORE-V Family of RISC-V Cores☆324Updated 11 months ago
- The next generation of OpenLane, rewritten from scratch with a modular architecture☆331Updated 2 months ago
- RISC-V Verification Interface☆138Updated last week
- This repo is a fork of the master OpenLANE repo for us with projects submitted on Efabless Open MPW or chipIgnite shuttles:: OpenLANE is …☆161Updated last year
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆246Updated 5 months ago
- Example LED blinking project for your FPGA dev board of choice☆189Updated 2 weeks ago
- HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V pro…☆111Updated last week