zeroasiccorp / switchboardLinks
Communication framework for RTL simulation and emulation.
☆304Updated this week
Alternatives and similar repositories for switchboard
Users that are interested in switchboard are comparing it to the libraries listed below
Sorting:
- Universal Memory Interface (UMI)☆153Updated 2 weeks ago
- CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…☆450Updated this week
- Fabric generator and CAD tools.☆209Updated this week
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆192Updated last week
- Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.☆366Updated 9 months ago
- 10Gb Ethernet Switch☆240Updated last month
- CORE-V Family of RISC-V Cores☆310Updated 9 months ago
- ASIC implementation flow infrastructure, successor to OpenLane☆200Updated this week
- Bringup-Bench is a collection of standalone minimal library and system dependence benchmarks useful for bringing up newly designed CPUs, …☆218Updated last month
- Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.☆258Updated 3 years ago
- This tool translates synthesizable SystemC code to synthesizable SystemVerilog.☆297Updated last month
- A hardware component library developed with ROHD.☆107Updated last month
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆302Updated last week
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆164Updated this week
- Waveform Viewer Extension for VScode☆289Updated this week
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆124Updated 5 months ago
- eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V☆228Updated last week
- Example designs showing different ways to use F4PGA toolchains.☆279Updated last year
- Standard Cell Library based Memory Compiler using FF/Latch cells☆163Updated last month
- ☆110Updated 2 years ago
- Open-source FPGA research and prototyping framework.☆210Updated last year
- ☆364Updated 2 years ago
- SystemVerilog synthesis tool☆220Updated 9 months ago
- RISC-V Verification Interface☆126Updated 2 weeks ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆238Updated 3 months ago
- FuseSoC standard core library☆149Updated 6 months ago
- The next generation of OpenLane, rewritten from scratch with a modular architecture☆321Updated last week
- SystemVerilog frontend for Yosys☆178Updated this week
- https://caravel-user-project.readthedocs.io☆223Updated 9 months ago
- Raptor end-to-end FPGA Compiler and GUI☆91Updated 11 months ago