Alternatives and similar repositories for switchboard

Users that are interested in switchboard are comparing it to the libraries listed below

• zeroasiccorp / umi
  Universal Memory Interface (UMI)
  ☆148Updated last week
• openhwgroup / cvw
  CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…
  ☆402Updated this week
• FPGA-Research / FABulous
  Fabric generator and CAD tools.
  ☆192Updated last week
• mattvenn / awesome-opensource-asic-resources
  ☆337Updated 2 years ago
• ZipCPU / eth10g
  10Gb Ethernet Switch
  ☆226Updated 3 months ago
• toddmaustin / bringup-bench
  Bringup-Bench is a collection of standalone minimal library and system dependence benchmarks useful for bringing up newly designed CPUs, …
  ☆183Updated 3 months ago
• efabless / caravel
  Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
  ☆343Updated 5 months ago
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆154Updated last month
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆105Updated 2 months ago
• intel / systemc-compiler
  This tool translates synthesizable SystemC code to synthesizable SystemVerilog.
  ☆281Updated 3 weeks ago
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆127Updated 2 weeks ago
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆184Updated 3 weeks ago
• SparcLab / OpenSERDES
  Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.
  ☆249Updated 3 years ago
• tenstorrent / riscv_arch_tests
  Self checking RISC-V directed tests
  ☆111Updated 2 months ago
• TL-X-org / TL-V_Projects
  An overview of TL-Verilog resources and projects
  ☆80Updated 4 months ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆117Updated 3 weeks ago
• esl-epfl / x-heep
  eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V
  ☆205Updated this week
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆148Updated last week
• aignacio / nox
  RISC-V Nox core
  ☆66Updated 2 weeks ago
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆206Updated 4 months ago
• NVlabs / GEM
  Open-source RTL logic simulator with CUDA acceleration
  ☆201Updated this week
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆146Updated 2 years ago
• HDLForBeginners / Examples
  ☆98Updated last year
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆100Updated 2 months ago
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆285Updated 5 months ago
• pulp-platform / carfield
  A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …
  ☆109Updated 2 weeks ago
• intel / rohd-hcl
  A hardware component library developed with ROHD.
  ☆99Updated last week
• os-fpga / Raptor
  Raptor end-to-end FPGA Compiler and GUI
  ☆84Updated 7 months ago
• efabless / openlane2
  The next generation of OpenLane, rewritten from scratch with a modular architecture
  ☆306Updated 5 months ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆93Updated this week