os-fpga / RaptorLinks
Raptor end-to-end FPGA Compiler and GUI
☆78Updated 5 months ago
Alternatives and similar repositories for Raptor
Users that are interested in Raptor are comparing it to the libraries listed below
Sorting:
- SystemVerilog frontend for Yosys☆117Updated last week
- A SystemVerilog source file pickler.☆57Updated 7 months ago
- ☆44Updated 2 months ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- Framework Open EDA Gui☆65Updated 5 months ago
- The multi-core cluster of a PULP system.☆97Updated last week
- Python script to transform a VCD file to wavedrom format☆77Updated 2 years ago
- FPGA tool performance profiling☆102Updated last year
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated last year
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆60Updated 4 months ago
- Library of open source Process Design Kits (PDKs)☆42Updated last week
- RISC-V Nox core☆62Updated 2 months ago
- HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V pro…☆51Updated 4 months ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆93Updated 9 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆105Updated 2 weeks ago
- Structural Netlist API (and more) for EDA post synthesis flow development☆103Updated last week
- Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments☆60Updated this week
- An automatic clock gating utility☆48Updated last month
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆89Updated this week
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆65Updated 5 months ago
- The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH…☆43Updated last month
- Limited python / cocotb interface to Xilinx/AMD Vivado simulator.☆43Updated 4 months ago
- Bitstream relocation and manipulation tool.☆46Updated 2 years ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆135Updated this week
- OSVVM Documentation☆34Updated 3 weeks ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆114Updated last year
- FuseSoC standard core library☆139Updated last week
- A command-line tool for displaying vcd waveforms.☆58Updated last year
- ☆25Updated this week
- ☆95Updated last year