os-fpga / Raptor
Raptor end-to-end FPGA Compiler and GUI
☆65Updated this week
Related projects ⓘ
Alternatives and complementary repositories for Raptor
- RISC-V Nox core☆61Updated 3 months ago
- FPGA tool performance profiling☆102Updated 8 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆67Updated 6 months ago
- Framework Open EDA Gui☆60Updated last week
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆110Updated last year
- A SystemVerilog source file pickler.☆51Updated last month
- Universal Memory Interface (UMI)☆141Updated last week
- Plugins for Yosys developed as part of the F4PGA project.☆81Updated 6 months ago
- WAL enables programmable waveform analysis.☆138Updated 3 weeks ago
- Drawio => VHDL and Verilog☆51Updated last year
- Version manager (and builder) for the Google sky130 and gf180mcu open-source PDKs☆63Updated last month
- A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …☆73Updated this week
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆73Updated 2 months ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆60Updated 5 months ago
- An automatic clock gating utility☆43Updated 4 months ago
- Mutation Cover with Yosys (MCY)☆77Updated 2 weeks ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆63Updated 7 months ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆133Updated 5 months ago
- FuseSoC standard core library☆115Updated last month
- Open source ISS and logic RISC-V 32 bit project☆40Updated this week
- Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments☆47Updated this week
- Generic Register Interface (contains various adapters)☆100Updated last month
- Spicing up the first and only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples. https://www.chil…☆46Updated 2 weeks ago
- Facilitates building open source tools for working with hardware description languages (HDLs)☆62Updated 4 years ago
- Sphinx Extension which generates various types of diagrams from Verilog code.☆55Updated last year
- A pipelined RISC-V processor☆47Updated 11 months ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆58Updated last month
- ☆76Updated 8 months ago
- ☆75Updated last year
- Prefix tree adder space exploration library☆55Updated this week