Alternatives and similar repositories for Raptor

Users that are interested in Raptor are comparing it to the libraries listed below

• os-fpga / FOEDAG
  Framework Open EDA Gui
  ☆68Updated 9 months ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆84Updated last year
• zeroasiccorp / umi
  Universal Memory Interface (UMI)
  ☆149Updated last week
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆106Updated last week
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆119Updated 2 months ago
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆102Updated last year
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆57Updated last year
• aignacio / nox
  RISC-V Nox core
  ☆68Updated last month
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆118Updated last year
• siliconcompiler / lambdapdk
  Library of open source Process Design Kits (PDKs)
  ☆51Updated this week
• najaeda / naja
  Structural Netlist API (and more) for EDA post synthesis flow development
  ☆113Updated this week
• pulp-platform / cheshire-ihp130-o
  ☆52Updated 5 months ago
• lip6 / coriolis
  Coriolis VLSI EDA Tool (LIP6)
  ☆70Updated this week
• IHP-GmbH / IHP-Open-DesignLib
  Open source designs developed with IHP 130nm BiCMOS Open Source PDK. Documentation at https://ihp-open-ip.readthedocs.io/en/latest/
  ☆58Updated 2 weeks ago
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆65Updated 7 months ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆60Updated 10 months ago
• IBM / hdl-tools
  Facilitates building open source tools for working with hardware description languages (HDLs)
  ☆65Updated 5 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆71Updated 2 months ago
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆155Updated 3 months ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆108Updated this week
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆47Updated 3 months ago
• mole99 / greyhound-ihp
  Greyhound on IHP SG13G2 0.13 μm BiCMOS process
  ☆56Updated this week
• siliconcompiler / scgallery
  SiliconCompiler Design Gallery
  ☆51Updated last week
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆50Updated 4 months ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆88Updated last month
• siliconcompiler / zerosoc
  Demo SoC for SiliconCompiler.
  ☆60Updated last week
• hdl / conda-eda
  Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.
  ☆102Updated 7 months ago
• efabless / sky130_sram_macros_old
  ☆38Updated 3 years ago
• efabless / caravel_user_project_analog
  ☆49Updated 7 months ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆157Updated this week