IntelLabs / FloorSetLinks
☆73Updated last month
Alternatives and similar repositories for FloorSet
Users that are interested in FloorSet are comparing it to the libraries listed below
Sorting:
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆82Updated 2 months ago
- Collection of digital hardware modules & projects (benchmarks)☆59Updated last week
- ☆76Updated 3 weeks ago
- GPU-based logic synthesis tool☆83Updated 3 weeks ago
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆105Updated last year
- ☆25Updated last year
- This GitHub repo is for the OpenROAD and CircuitOps Tutorial at ASP-DAC 2024☆51Updated 5 months ago
- This is a python repo for flattening Verilog☆18Updated 2 months ago
- ☆52Updated last month
- EDA physical synthesis optimization kit☆59Updated last year
- DATC Robust Design Flow.☆37Updated 5 years ago
- ☆105Updated 5 years ago
- UCSD Detailed Router☆89Updated 4 years ago
- DATC RDF☆51Updated 4 years ago
- ☆31Updated 2 years ago
- ☆44Updated last year
- ☆86Updated 3 weeks ago
- ☆50Updated last month
- CUGR, VLSI Global Routing Tool Developed by CUHK☆137Updated 2 years ago
- The first version of TritonPart☆27Updated last year
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆52Updated last month
- ☆25Updated 4 years ago
- Material for OpenROAD Tutorial at DAC 2020☆47Updated 2 years ago
- IDEA project source files☆107Updated 8 months ago
- ☆29Updated last year
- ☆31Updated 3 years ago
- Library for VLSI CAD Design Useful parsers and solvers' api are implemented.☆171Updated last month
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆52Updated 6 months ago
- ☆39Updated 2 years ago
- Dr. CU, VLSI Detailed Routing Tool Developed by CUHK☆135Updated 2 years ago