cuhk-eda / GCS-TimerLinks
☆26Updated 2 months ago
Alternatives and similar repositories for GCS-Timer
Users that are interested in GCS-Timer are comparing it to the libraries listed below
Sorting:
- GPU-based logic synthesis tool☆97Updated 2 months ago
- Xplace 3.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability and Timing Optimization☆156Updated 3 weeks ago
- Hypergraph Partitioning: benchmarks, evaluators, best known solutions and codes☆76Updated 3 weeks ago
- The first version of TritonPart☆31Updated 2 years ago
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆109Updated last year
- ☆42Updated 3 years ago
- ☆15Updated last year
- Official implementation of DATE'25 paper "Timing-Driven Global Placement by Efficient Critical Path Extraction".☆62Updated 7 months ago
- Official implementation of paper "Open3DBench: Open-Source Benchmark for 3D-IC Backend Implementation and PPA Evaluation".☆79Updated 7 months ago
- ☆36Updated 5 years ago
- ☆50Updated 2 years ago
- [ICCAD 22]DeePEB: A neural network based PEB solver☆11Updated 2 years ago
- Official open source repository for "A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction" (DAC 2022)☆88Updated last year
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆91Updated 9 months ago
- Pin-Accessible Legalization for Mixed-Cell-Height Circuits☆31Updated 3 years ago
- CUGR, VLSI Global Routing Tool Developed by CUHK☆142Updated 2 years ago
- ☆23Updated last year
- ☆95Updated 7 months ago
- Library for VLSI CAD Design Useful parsers and solvers' api are implemented.☆190Updated 8 months ago
- Official implementation of MacroRank: Ranking Macro Placement Solutions Leveraging Translation Equivariancy (ASP-DAC 2023)☆17Updated 2 years ago
- Rsyn – An Extensible Physical Synthesis Framework☆137Updated last year
- ☆40Updated 4 years ago
- Dr. CU, VLSI Detailed Routing Tool Developed by CUHK☆142Updated 2 years ago
- Collection of digital hardware modules & projects (benchmarks)☆80Updated 2 months ago
- A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…☆39Updated last month
- GPU-Accelerated Global Router☆28Updated last year
- ☆13Updated last year
- A High-performance Timing Analysis Tool for VLSI Systems☆10Updated 4 years ago
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆66Updated 8 months ago
- ☆97Updated 7 months ago