cuhk-eda / GCS-TimerLinks
☆24Updated 5 months ago
Alternatives and similar repositories for GCS-Timer
Users that are interested in GCS-Timer are comparing it to the libraries listed below
Sorting:
- Hypergraph Partitioning: benchmarks, evaluators, best known solutions and codes☆75Updated 3 weeks ago
- GPU-based logic synthesis tool☆93Updated last week
- Xplace 3.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability and Timing Optimization☆142Updated 5 months ago
- The first version of TritonPart☆29Updated last year
- ☆14Updated last year
- ☆34Updated 5 years ago
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆107Updated last year
- ☆40Updated 2 years ago
- Official open source repository for "A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction" (DAC 2022)☆82Updated last year
- Official implementation of DATE'25 paper "Timing-Driven Global Placement by Efficient Critical Path Extraction".☆55Updated 5 months ago
- Official implementation of paper "Open3DBench: Open-Source Benchmark for 3D-IC Backend Implementation and PPA Evaluation".☆66Updated 5 months ago
- Pin-Accessible Legalization for Mixed-Cell-Height Circuits☆29Updated 3 years ago
- ☆47Updated last year
- [ICCAD 22]DeePEB: A neural network based PEB solver☆11Updated 2 years ago
- ☆89Updated 5 months ago
- Rsyn – An Extensible Physical Synthesis Framework☆132Updated last year
- Collection of digital hardware modules & projects (benchmarks)☆69Updated last week
- ☆21Updated 11 months ago
- ☆10Updated 3 years ago
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆86Updated 6 months ago
- ☆31Updated last year
- CUGR, VLSI Global Routing Tool Developed by CUHK☆138Updated 2 years ago
- Library for VLSI CAD Design Useful parsers and solvers' api are implemented.☆186Updated 6 months ago
- ☆25Updated last year
- A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…☆36Updated 4 months ago
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆58Updated 5 months ago
- Dr. CU, VLSI Detailed Routing Tool Developed by CUHK☆138Updated 2 years ago
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆54Updated 10 months ago
- Reimplementation of the VLSI placement algorithm: ePlace and ePlace-MS☆53Updated last year
- Artificial Netlist Generator☆44Updated last year