A standalone structural (gate-level) verilog parser
☆41Jul 16, 2026Updated last week
Alternatives and similar repositories for naja-verilog
Users that are interested in naja-verilog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Netlist API (and more) for EDA flow development☆150Updated this week
- A Standalone Structural Verilog Parser☆98Mar 31, 2022Updated 4 years ago
- Java library for parsing and manipulating graph representations of gate-level Verilog netlists☆15Jan 9, 2017Updated 9 years ago
- ☆14Jan 3, 2018Updated 8 years ago
- Random Generator of Btor2 Files☆10Sep 2, 2023Updated 2 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- A Lean-embedded framework to verify Verilog modules☆15Jul 3, 2026Updated 3 weeks ago
- QuteRTL: A RTL Front-End Towards Intelligent Synthesis and Verification☆18Nov 8, 2016Updated 9 years ago
- LLM4HWDesign Starting Toolkit☆20Oct 4, 2024Updated last year
- Control Logic Synthesis: Drawing the Rest of the OWL☆13Jun 17, 2024Updated 2 years ago
- Collection of utlities for writing parsers. Includes a fast DIMACS CNF parser.☆15Nov 19, 2024Updated last year
- AMulet 2. - A better AIG Multiplier Examination Tool☆30Dec 23, 2025Updated 7 months ago
- Using e-graphs to synthesize netlists from boolean logic.☆14Jul 26, 2023Updated 3 years ago
- ☆16Jul 3, 2023Updated 3 years ago
- easter egg is a flexible, high-performance e-graph library with support of multiple additional assumptions at once☆13Mar 27, 2025Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Digital Design Equivalence Checking☆81Updated this week
- A fork of the Kissat SAT solver with additional features. Supports incremental solving.☆16Aug 13, 2022Updated 3 years ago
- Integer Multiplier Generator for Verilog☆25Jul 4, 2025Updated last year
- SystemVerilog design elaborator into word-level netlist form☆243Updated this week
- Refreshing automation for inductive equational proofs using e-graphs☆28Jul 7, 2024Updated 2 years ago
- ☆15Oct 8, 2024Updated last year
- ☆24Jul 19, 2026Updated last week
- Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation (ICCAD 2024)☆40Jun 17, 2025Updated last year
- egraph <-> json☆17Dec 29, 2025Updated 7 months ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- E-morphic: Scalable Equality Saturation for Structural Exploration in Logic Synthesis (DAC2025)☆29Jun 23, 2025Updated last year
- Fast Symbolic Repair of Hardware Design Code☆39Jan 20, 2025Updated last year
- This repository contains an example of the connection between an UVM Testbench and a Python reference model using UVM Connect from Mentor…☆17Feb 21, 2020Updated 6 years ago
- ☆47Jan 22, 2026Updated 6 months ago
- cpp parser for reading a VCD (value change dump) file☆10Jul 15, 2013Updated 13 years ago
- BTOR2 MLIR project☆26Jan 17, 2024Updated 2 years ago
- AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining☆20Nov 1, 2022Updated 3 years ago
- MLIR+EqSat☆28Jan 10, 2026Updated 6 months ago
- Python version of tools to work with AIG formatted files☆12May 20, 2025Updated last year
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- APS: An open-source toolchain towards agile processor specialization based on MLIR☆19Jan 17, 2026Updated 6 months ago
- ☆19Dec 21, 2020Updated 5 years ago
- ☆36Apr 22, 2026Updated 3 months ago
- Cell layout generation (MH Multiheight) for DTCO/STCO exploration toolkit.☆15Oct 6, 2025Updated 9 months ago
- Embedded UVM (D Language port of IEEE UVM 1.0)☆34Nov 6, 2025Updated 8 months ago
- Using e-graphs for logic synthesis (ICCAD'25)☆35Updated this week
- ideas and eda software for vlsi design☆51Updated this week