Alternatives and similar repositories for naja-verilog

Users that are interested in naja-verilog are comparing it to the libraries listed below

• lac-dcc / chimera
  A tool for synthesizing Verilog programs
  ☆107Updated 2 months ago
• Nic30 / hwtHls
  LLVM based HLS library for HWToolkit (hardware devel. toolkit)
  ☆25Updated last week
• amamory-verification / hw-formal-verif
  Hardware Formal Verification
  ☆16Updated 5 years ago
• circuitgraph / circuitgraph
  Tools for working with circuits as graphs in python
  ☆126Updated 2 years ago
• leonardt / fault
  A Python package for testing hardware (part of the magma ecosystem)
  ☆46Updated last year
• pulp-platform / ELAU
  ☆20Updated last year
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆43Updated 2 years ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆43Updated 2 years ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated last year
• ckchengucsd / SMT-based-STDCELL-Layout-Generator-for-PROBE2.0
  SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis for PROBE 2.0
  ☆18Updated 5 years ago
• YosysHQ / eqy
  Equivalence checking with Yosys
  ☆51Updated last week
• tdb-alcorn / chisel-formal
  ☆23Updated 4 years ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆51Updated 7 months ago
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆92Updated last year
• dian-lun-lin / RTLflow
  A GPU acceleration flow for RTL simulation with batch stimulus
  ☆115Updated last year
• cclienti / svmodule
  SystemVerilog & Verilog Module I/O parser and printer
  ☆25Updated 4 years ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆28Updated 3 years ago
• amahzoon / genmul
  ☆18Updated 4 years ago
• najaeda / naja
  Structural Netlist API (and more) for EDA post synthesis flow development
  ☆120Updated this week
• The-OpenROAD-Project / alpha-release
  Builds, flow and designs for the alpha release
  ☆54Updated 5 years ago
• scale-lab / BLASYS
  An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization
  ☆32Updated 2 years ago
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆88Updated last year
• snishizawa / asap7_snps
  Supplemental technology files for ASAP7 PDK with Synopsys design flow
  ☆19Updated 2 years ago
• openformal / sva_basics
  This repository is compilation of basics of System Verilog Assertions in context of formal verification
  ☆24Updated 6 years ago
• aolofsson / POSH
  ☆44Updated 5 years ago
• ekiwi / rtl-repair
  Fast Symbolic Repair of Hardware Design Code
  ☆28Updated 10 months ago
• pulp-platform / cheshire-ihp130-o
  ☆58Updated 7 months ago
• woset-workshop / woset-workshop.github.io
  Workshop on Open-Source EDA Technology (WOSET)
  ☆48Updated last year
• jinwookjungs / open_design_flow
  OpenDesign Flow Database
  ☆16Updated 7 years ago
• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆32Updated 2 years ago