najaeda / naja-verilog
A standalone structural (gate-level) verilog parser
☆35Updated 4 months ago
Alternatives and similar repositories for naja-verilog:
Users that are interested in naja-verilog are comparing it to the libraries listed below
- Builds, flow and designs for the alpha release☆54Updated 5 years ago
- An automatic clock gating utility☆46Updated last week
- ☆55Updated 2 years ago
- Equivalence checking with Yosys☆42Updated last week
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆40Updated 2 years ago
- Structural Netlist API (and more) for EDA post synthesis flow development☆93Updated last week
- ☆35Updated 3 weeks ago
- A Standalone Structural Verilog Parser☆91Updated 3 years ago
- Raptor end-to-end FPGA Compiler and GUI☆77Updated 4 months ago
- Fast Symbolic Repair of Hardware Design Code☆22Updated 3 months ago
- Cross EDA Abstraction and Automation☆36Updated last week
- Tools for working with circuits as graphs in python☆115Updated last year
- SystemVerilog frontend for Yosys☆91Updated this week
- Library of open source Process Design Kits (PDKs)☆37Updated this week
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆33Updated 5 months ago
- ☆31Updated 3 months ago
- Collection of test cases for Yosys☆18Updated 3 years ago
- Source codes and calibration scripts for clock tree synthesis☆40Updated 5 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆49Updated 9 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 4 years ago
- A tool for synthesizing Verilog programs☆77Updated this week
- Workshop on Open-Source EDA Technology (WOSET)☆49Updated 5 months ago
- This repository is compilation of basics of System Verilog Assertions in context of formal verification☆20Updated 6 years ago
- FPGA tool performance profiling☆102Updated last year
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 4 years ago
- Benchmarks for Yosys development☆24Updated 5 years ago
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆58Updated 3 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated 11 months ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 4 years ago
- ☆43Updated 5 years ago