najaeda / naja-verilogLinks
A standalone structural (gate-level) verilog parser
☆38Updated 3 weeks ago
Alternatives and similar repositories for naja-verilog
Users that are interested in naja-verilog are comparing it to the libraries listed below
Sorting:
- A tool for synthesizing Verilog programs☆95Updated last week
- LLVM based HLS library for HWToolkit (hardware devel. toolkit)☆25Updated 3 weeks ago
- Tools for working with circuits as graphs in python☆122Updated last year
- Hardware Formal Verification☆15Updated 5 years ago
- Equivalence checking with Yosys☆45Updated this week
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆42Updated 2 years ago
- ☆23Updated 4 years ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆33Updated 2 months ago
- A Python package for testing hardware (part of the magma ecosystem)☆43Updated last year
- ☆19Updated last year
- YosysHQ SVA AXI Properties☆42Updated 2 years ago
- SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis for PROBE 2.0☆18Updated 5 years ago
- Builds, flow and designs for the alpha release☆54Updated 5 years ago
- An automatic clock gating utility☆50Updated 3 months ago
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆110Updated 2 months ago
- ☆32Updated 7 months ago
- SystemVerilog & Verilog Module I/O parser and printer☆25Updated 4 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆87Updated last year
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆83Updated 10 months ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- A GPU acceleration flow for RTL simulation with batch stimulus☆113Updated last year
- An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization☆31Updated last year
- OpenDesign Flow Database☆16Updated 6 years ago
- Simple UVM environment for experimenting with Verilator.☆23Updated 3 months ago
- ☆48Updated 4 months ago
- QuteRTL: A RTL Front-End Towards Intelligent Synthesis and Verification☆16Updated 8 years ago
- A library and command-line tool for querying a Verilog netlist.☆27Updated 3 years ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆37Updated last month
- Workshop on Open-Source EDA Technology (WOSET)☆48Updated 8 months ago
- A SystemVerilog source file pickler.☆59Updated 9 months ago