Alternatives and similar repositories for naja-verilog

Users that are interested in naja-verilog are comparing it to the libraries listed below

• The-OpenROAD-Project / alpha-release
  Builds, flow and designs for the alpha release
  ☆54Updated 5 years ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆42Updated 2 years ago
• pulp-platform / cheshire-ihp130-o
  ☆47Updated 2 months ago
• najaeda / naja
  Structural Netlist API (and more) for EDA post synthesis flow development
  ☆107Updated this week
• pulp-platform / ELAU
  ☆18Updated last year
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆49Updated 2 months ago
• ekiwi / rtl-repair
  Fast Symbolic Repair of Hardware Design Code
  ☆24Updated 5 months ago
• Xilinx / fpga24_routing_contest
  Runtime-First FPGA Interchange Routing Contest @ FPGA’24
  ☆33Updated 3 weeks ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆57Updated 8 months ago
• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆28Updated 2 years ago
• verilator / uvm
  Universal Verification Methodology (UVM) base libraries, with edits for Verilator
  ☆27Updated 5 years ago
• YosysHQ / eqy
  Equivalence checking with Yosys
  ☆45Updated 2 weeks ago
• siliconcompiler / lambdapdk
  Library of open source Process Design Kits (PDKs)
  ☆47Updated last week
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated last year
• YosysHQ / yosys-tests
  Collection of test cases for Yosys
  ☆18Updated 3 years ago
• The-OpenROAD-Project / megaboom
  ☆27Updated this week
• pulp-platform / svase
  ☆32Updated 5 months ago
• woset-workshop / woset-workshop.github.io
  Workshop on Open-Source EDA Technology (WOSET)
  ☆49Updated 7 months ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆71Updated last year
• chipsalliance / fpga-interchange-schema
  ☆56Updated 2 years ago
• NVlabs / GL0AM
  GL0AM GPU Accelerated Gate Level Logic Simulator
  ☆18Updated 2 weeks ago
• greenblat / vlsistuff
  ideas and eda software for vlsi design
  ☆50Updated this week
• jinwookjungs / open_design_flow
  OpenDesign Flow Database
  ☆16Updated 6 years ago
• chipsalliance / UHDM-integration-tests
  ☆31Updated last year
• idea-fasoc / fasoc
  ☆54Updated last year
• aolofsson / POSH
  ☆44Updated 5 years ago
• dan-fritchman / Hdl21
  Hardware Description Library
  ☆80Updated 2 months ago
• MikeCovrado / GettingVerilatorStartedWithUVM
  Simple UVM environment for experimenting with Verilator.
  ☆21Updated last month
• RIOSLaboratory / OpenRPDK28
  Open source process design kit for 28nm open process
  ☆59Updated last year
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆84Updated 2 weeks ago