Alternatives and similar repositories for naja-verilog

Users that are interested in naja-verilog are comparing it to the libraries listed below

• The-OpenROAD-Project / alpha-release
  Builds, flow and designs for the alpha release
  ☆54Updated 5 years ago
• pulp-platform / ELAU
  ☆18Updated 11 months ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆41Updated 2 years ago
• pulp-platform / cheshire-ihp130-o
  ☆44Updated 2 months ago
• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆27Updated 2 years ago
• YosysHQ / eqy
  Equivalence checking with Yosys
  ☆43Updated 3 weeks ago
• pulp-platform / svase
  ☆32Updated 4 months ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆48Updated last month
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆71Updated last year
• siliconcompiler / lambdapdk
  Library of open source Process Design Kits (PDKs)
  ☆42Updated this week
• rahulk29 / sram22
  A configurable SRAM generator
  ☆50Updated this week
• chipsalliance / fpga-interchange-schema
  ☆56Updated 2 years ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆27Updated 2 years ago
• openformal / sva_basics
  This repository is compilation of basics of System Verilog Assertions in context of formal verification
  ☆21Updated 6 years ago
• Nic30 / hdlConvertorAst
  Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
  ☆35Updated last week
• woset-workshop / woset-workshop.github.io
  Workshop on Open-Source EDA Technology (WOSET)
  ☆49Updated 6 months ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆39Updated 2 years ago
• ekiwi / rtl-repair
  Fast Symbolic Repair of Hardware Design Code
  ☆23Updated 4 months ago
• najaeda / naja
  Structural Netlist API (and more) for EDA post synthesis flow development
  ☆103Updated last week
• accellera-official / crave
  Constrained RAndom Verification Enviroment (CRAVE)
  ☆17Updated last year
• ucb-substrate / substrate2
  21st century electronic design automation tools, written in Rust.
  ☆30Updated last week
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆83Updated last year
• leonardt / fault
  A Python package for testing hardware (part of the magma ecosystem)
  ☆43Updated last year
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆83Updated 3 weeks ago
• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆38Updated last week
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated last year
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆117Updated last week
• Xilinx / fpga24_routing_contest
  Runtime-First FPGA Interchange Routing Contest @ FPGA’24
  ☆33Updated this week
• MikeCovrado / GettingVerilatorStartedWithUVM
  Simple UVM environment for experimenting with Verilator.
  ☆21Updated last month
• snishizawa / libretto
  Characterizer
  ☆23Updated 2 weeks ago