Alternatives and similar repositories for nexus

Users that are interested in nexus are comparing it to the libraries listed below

• pulp-platform / svase
  ☆33Updated 11 months ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 6 months ago
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆96Updated last year
• bespoke-silicon-group / bsg_fakeram
  fakeram generator for use by researchers who do not have access to commercial ram generators
  ☆38Updated 2 years ago
• esa-tu-darmstadt / SCAIE-V-2.0
  ☆21Updated last month
• Intuity / forastero
  Making cocotb testbenches that bit easier
  ☆36Updated 2 months ago
• rahulk29 / sram22
  A configurable SRAM generator
  ☆56Updated 4 months ago
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆31Updated 8 months ago
• Nic30 / hdlConvertorAst
  Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
  ☆41Updated last month
• openecos-projects / icsprout55-pdk
  55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd.
  ☆148Updated last week
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆94Updated last month
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆43Updated 2 years ago
• dian-lun-lin / RTLflow
  A GPU acceleration flow for RTL simulation with batch stimulus
  ☆116Updated last year
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆44Updated 2 years ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆77Updated 5 months ago
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆88Updated last year
• cornell-brg / pymtl3-net
  Project repo for the POSH on-chip network generator
  ☆52Updated 9 months ago
• chipsalliance / UHDM-integration-tests
  ☆31Updated 2 years ago
• Silimate / prunefl
  SystemVerilog file list pruner
  ☆16Updated last month
• antmicro / verilator-verification
  Test dashboard for verification features in Verilator
  ☆28Updated this week
• accellera-official / PySysC
  Public repository for PySysC, (From SC Common Practices Subgroup)
  ☆54Updated 2 years ago
• pulp-platform / cheshire-ihp130-o
  ☆58Updated 9 months ago
• bensampson5 / libsv
  An open source, parameterized SystemVerilog digital hardware IP library
  ☆30Updated last year
• qleenju / PDPU
  PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications
  ☆43Updated 2 years ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆186Updated this week
• fvutils / pyhdl-if
  Python interface for cross-calling with HDL
  ☆45Updated last week
• riscv-verification / riscvISACOV
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆33Updated 3 weeks ago
• spider-tronix / Standard-Cell-Characterization
  Open Source tool to build liberty files and for Characterizing Standard Cells.
  ☆28Updated 4 years ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆51Updated 8 months ago
• chipsalliance / uvm-verilator
  ☆110Updated last month