Intuity / nexusLinks
Open source RTL simulation acceleration on commodity hardware
☆34Updated 2 years ago
Alternatives and similar repositories for nexus
Users that are interested in nexus are comparing it to the libraries listed below
Sorting:
- Making cocotb testbenches that bit easier☆36Updated 3 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 7 months ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆117Updated last year
- YosysHQ SVA AXI Properties☆43Updated 3 years ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆37Updated 3 years ago
- ☆33Updated last year
- Scalable Interface for RISC-V ISA Extensions☆23Updated this week
- SystemVerilog Linter based on pyslang☆31Updated 9 months ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆98Updated 2 months ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆98Updated last year
- A configurable SRAM generator☆58Updated 5 months ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆77Updated 6 months ago
- Project repo for the POSH on-chip network generator☆52Updated 10 months ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆41Updated 2 months ago
- Python interface for cross-calling with HDL☆47Updated 2 weeks ago
- Test dashboard for verification features in Verilator☆29Updated this week
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆88Updated last year
- Public repository for PySysC, (From SC Common Practices Subgroup)☆54Updated 2 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆33Updated last month
- 55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd.☆166Updated last month
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- ☆31Updated 2 years ago
- Constrained RAndom Verification Enviroment (CRAVE)☆18Updated 2 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆55Updated 6 years ago
- A SystemVerilog source file pickler.☆60Updated last year
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆43Updated last month
- Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats☆51Updated 5 years ago
- Python library for operations with VCD and other digital wave files☆54Updated 2 months ago
- Open source process design kit for 28nm open process☆72Updated last year
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆81Updated last month