Intuity / nexusLinks
Open source RTL simulation acceleration on commodity hardware
☆34Updated 2 years ago
Alternatives and similar repositories for nexus
Users that are interested in nexus are comparing it to the libraries listed below
Sorting:
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 7 months ago
- ☆33Updated last year
- Scalable Interface for RISC-V ISA Extensions☆23Updated this week
- A GPU acceleration flow for RTL simulation with batch stimulus☆117Updated last year
- fakeram generator for use by researchers who do not have access to commercial ram generators☆37Updated 3 years ago
- Making cocotb testbenches that bit easier☆36Updated 3 months ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆88Updated last year
- A configurable SRAM generator☆58Updated 5 months ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆98Updated last year
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆98Updated 2 months ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆35Updated 8 months ago
- 55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd.☆167Updated last month
- Project repo for the POSH on-chip network generator☆52Updated 10 months ago
- YosysHQ SVA AXI Properties☆43Updated 3 years ago
- Public repository for PySysC, (From SC Common Practices Subgroup)☆54Updated 2 years ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆41Updated 2 months ago
- ☆31Updated 2 years ago
- A SystemVerilog source file pickler.☆60Updated last year
- Constrained RAndom Verification Enviroment (CRAVE)☆18Updated 2 years ago
- SystemVerilog Linter based on pyslang☆31Updated 9 months ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆43Updated last month
- Python interface for cross-calling with HDL☆47Updated 2 weeks ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆23Updated 2 weeks ago
- ☆44Updated 6 years ago
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆28Updated 4 years ago
- Workshop on Open-Source EDA Technology (WOSET)☆48Updated last year
- RISC-V Nox core☆71Updated 6 months ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆48Updated last month
- Test dashboard for verification features in Verilator☆29Updated this week