Intuity / nexusLinks
Open source RTL simulation acceleration on commodity hardware
☆28Updated 2 years ago
Alternatives and similar repositories for nexus
Users that are interested in nexus are comparing it to the libraries listed below
Sorting:
- ☆32Updated 5 months ago
- Making cocotb testbenches that bit easier☆33Updated last week
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated last year
- SystemVerilog Linter based on pyslang☆31Updated last month
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆70Updated 9 months ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 5 years ago
- A configurable SRAM generator☆51Updated last week
- SystemVerilog Functional Coverage for RISC-V ISA☆28Updated 3 weeks ago
- Constrained RAndom Verification Enviroment (CRAVE)☆17Updated last year
- fakeram generator for use by researchers who do not have access to commercial ram generators☆37Updated 2 years ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆82Updated 8 months ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆83Updated last year
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- ☆44Updated 5 years ago
- ☆31Updated last year
- YosysHQ SVA AXI Properties☆40Updated 2 years ago
- CMake based hardware build system☆27Updated this week
- An open source, parameterized SystemVerilog digital hardware IP library☆27Updated last year
- An opinionated build environment for EDA projects☆19Updated 2 months ago
- ☆15Updated 2 weeks ago
- Python interface for cross-calling with HDL☆32Updated 2 weeks ago
- RISC-V Nox core☆64Updated 3 months ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆33Updated 3 weeks ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆33Updated last week
- ☆18Updated last year
- DUTH RISC-V Superscalar Microprocessor☆31Updated 8 months ago
- ☆46Updated 2 months ago
- An automatic clock gating utility☆49Updated 2 months ago
- SRAM☆22Updated 4 years ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆36Updated 2 weeks ago