Open source RTL simulation acceleration on commodity hardware
☆34Apr 13, 2023Updated 2 years ago
Alternatives and similar repositories for nexus
Users that are interested in nexus are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Making cocotb testbenches that bit easier☆38Feb 28, 2026Updated last month
- A suite of tools for pretty printing, diffing, and exploring abstract syntax trees.☆15Mar 3, 2026Updated last month
- SpiceBind – spice inside HDL simulator☆58Jun 30, 2025Updated 9 months ago
- GL0AM GPU Accelerated Gate Level Logic Simulator☆31Feb 11, 2026Updated last month
- An opinionated build environment for EDA projects☆19Jul 20, 2025Updated 8 months ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- ☆19Oct 7, 2025Updated 6 months ago
- StateMover is a checkpoint-based debugging framework for FPGAs.☆22Jul 14, 2022Updated 3 years ago
- Bluespec H.264 Decoder☆12Jul 17, 2014Updated 11 years ago
- SCARV: a side-channel hardened RISC-V platform☆28Jan 11, 2023Updated 3 years ago
- USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL☆32Oct 15, 2024Updated last year
- Hardware Design, Exploration, and Code Generation for SoC Designers☆12Dec 15, 2019Updated 6 years ago
- The official repository of metro-mpi☆18Sep 3, 2025Updated 7 months ago
- Examples of unions, interfaces, and assertions in SystemVerilog☆13Aug 31, 2013Updated 12 years ago
- Proposal to define an XML-based logging format for outputs from EDA tools and logging libraries.☆14Feb 24, 2026Updated last month
- DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Li…☆26Updated this week
- A GPU acceleration flow for RTL simulation with batch stimulus☆120Apr 1, 2024Updated 2 years ago
- Learn, share and collaborate on ASIC design using open tools and technologies☆14Dec 27, 2020Updated 5 years ago
- A Python package for creating and solving constrained randomization problems.☆18Oct 14, 2024Updated last year
- Hardware transactions library for Amaranth☆26Apr 2, 2026Updated last week
- Common Agent is a generic agent implemented in SystemVerilog, based on UVM methodology, which can be easily extended to create very fast …☆13Apr 29, 2015Updated 10 years ago
- Scalable Interface for RISC-V ISA Extensions☆25Updated this week
- SystemVerilog frontend for Yosys☆211Apr 2, 2026Updated last week
- Python bindings for slang, a library for compiling SystemVerilog☆66Jan 18, 2025Updated last year
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- An example model of a Network Processing Unit using the PFPSim framework.☆13Aug 23, 2016Updated 9 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Jun 28, 2025Updated 9 months ago
- ☆19Apr 10, 2014Updated 11 years ago
- chipy hdl☆17Apr 5, 2018Updated 8 years ago
- Arrow Matrix Decomposition - Communication-Efficient Distributed Sparse Matrix Multiplication☆15Mar 25, 2024Updated 2 years ago
- ☆14Aug 27, 2020Updated 5 years ago
- high-performance RTL simulator☆190Jun 19, 2024Updated last year
- Open-source RTL logic simulator with CUDA acceleration☆264Sep 30, 2025Updated 6 months ago
- ☆30Oct 16, 2022Updated 3 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Open source Logic Analyzer based on LiteX SoC☆27Apr 12, 2025Updated 11 months ago
- Mutation Cover with Yosys (MCY)☆91Mar 4, 2026Updated last month
- Tiny MATLAB-to-C converter (TMC Compiler)☆13Oct 26, 2020Updated 5 years ago
- Amazon F1-inspired Xilinx VCU118 hardware design framework☆13Jan 4, 2021Updated 5 years ago
- This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…☆18Nov 15, 2019Updated 6 years ago
- Parendi: Thousand-way Parallel RTL Simulation on the Graphcore IPU☆25Nov 26, 2025Updated 4 months ago
- Python interface for cross-calling with HDL☆49Mar 14, 2026Updated 3 weeks ago