siliconcompiler / logiklibLinks
Library of FPGA architectures
☆22Updated this week
Alternatives and similar repositories for logiklib
Users that are interested in logiklib are comparing it to the libraries listed below
Sorting:
- ☆33Updated 2 years ago
- Small footprint and configurable Inter-Chip communication cores☆59Updated last month
- RISC-V Processor written in Amaranth HDL☆38Updated 3 years ago
- USB virtual model in C++ for Verilog☆31Updated 8 months ago
- IRSIM switch-level simulator for digital circuits☆34Updated 2 months ago
- Automated Git mirror of Gaisler's GRLIB/Leon3 releases☆17Updated 3 months ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆33Updated 2 weeks ago
- Project aimed at implementing floating point operators using the DSP48E1 slice.☆29Updated 12 years ago
- Reusable Verilog 2005 components for FPGA designs☆44Updated 4 months ago
- Benchmarks for Yosys development☆24Updated 5 years ago
- Dual-issue RV64IM processor for fun & learning☆60Updated last year
- SiliconCompiler Design Gallery☆50Updated this week
- Greyhound on IHP SG13G2 0.13 μm BiCMOS process☆41Updated 2 weeks ago
- IEEE 754 single precision floating point library in systemverilog and vhdl☆30Updated 6 months ago
- A padring generator for ASICs☆25Updated 2 years ago
- ☆37Updated 2 years ago
- LunaPnR is a place and router for integrated circuits☆47Updated 7 months ago
- An automatic clock gating utility☆49Updated 2 months ago
- SoftCPU/SoC engine-V☆54Updated 3 months ago
- ☆47Updated 2 months ago
- Latest in the line of the E32 processors with better/generic cache placement☆10Updated 2 years ago
- ☆22Updated last month
- Bitstream relocation and manipulation tool.☆47Updated 2 years ago
- Experimental FPGA project for streaming two MIPI CSI camera streams to an HDMI monitor using a ULX3S FPGA board☆30Updated 2 years ago
- Small SERV-based SoC primarily for OpenMPW tapeout☆43Updated 3 weeks ago
- a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface☆32Updated 3 years ago
- RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).☆18Updated this week
- A pipelined RISC-V processor☆57Updated last year
- Library of open source Process Design Kits (PDKs)☆47Updated this week
- Specification of the Wishbone SoC Interconnect Architecture☆45Updated 3 years ago