Alternatives and similar repositories for logiklib

Users that are interested in logiklib are comparing it to the libraries listed below

• zephray / RISu064
  Dual-issue RV64IM processor for fun & learning
  ☆64Updated 2 years ago
• RTimothyEdwards / irsim
  IRSIM switch-level simulator for digital circuits
  ☆34Updated 5 months ago
• wyvernSemi / usbModel
  USB virtual model in C++ for Verilog
  ☆31Updated 11 months ago
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆48Updated 3 months ago
• asicsforthemasses / LunaPnR
  LunaPnR is a place and router for integrated circuits
  ☆47Updated 2 months ago
• pulp-platform / cheshire-ihp130-o
  ☆53Updated 6 months ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆61Updated 3 months ago
• clairexen / picorv
  PicoRV
  ☆44Updated 5 years ago
• TUT-ASI / leon3-grlib-gpl-mirror
  Automated Git mirror of Gaisler's GRLIB/Leon3 releases
  ☆20Updated 2 months ago
• siliconcompiler / scgallery
  SiliconCompiler Design Gallery
  ☆51Updated last week
• GuzTech / misato
  RISC-V Processor written in Amaranth HDL
  ☆39Updated 3 years ago
• b224hisl / rioschip
  ☆33Updated 2 years ago
• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆24Updated 5 years ago
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆36Updated 3 weeks ago
• fbrosser / DSP48E1-FP
  Project aimed at implementing floating point operators using the DSP48E1 slice.
  ☆29Updated 12 years ago
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆47Updated 2 years ago
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆106Updated 3 weeks ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• lip6 / coriolis
  Coriolis VLSI EDA Tool (LIP6)
  ☆72Updated 3 weeks ago
• efabless / sky130_sram_macros_old
  ☆38Updated 3 years ago
• aignacio / nox
  RISC-V Nox core
  ☆68Updated 2 months ago
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆51Updated 2 years ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆67Updated 2 weeks ago
• ultraembedded / core_usb_host
  Basic USB 1.1 Host Controller for small FPGAs
  ☆95Updated 5 years ago
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆87Updated 3 weeks ago
• amichai-bd / riscv-multi-core-lotr
  RISCV core RV32I/E.4 threads in a ring architecture
  ☆32Updated 2 years ago
• www-asics-ws / usb1_device
  USB 1.1 Device IP Core
  ☆21Updated 8 years ago
• IHP-GmbH / IHP-Open-DesignLib
  Open source designs developed with IHP 130nm BiCMOS Open Source PDK. Documentation at https://ihp-open-ip.readthedocs.io/en/latest/
  ☆59Updated last month
• asinghani / sky130-chip-vis
  Gate-level visualization generator for SKY130-based chip designs.
  ☆21Updated 4 years ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated last year