Library of FPGA architectures
☆33Apr 13, 2026Updated last month
Alternatives and similar repositories for logiklib
Users that are interested in logiklib are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- VS Code extension for SystemVerilog design navigation and RTL tracing. Seamlessly integrates with waveform viewer for post-simulation deb…☆37Nov 6, 2025Updated 6 months ago
- 9 track standard cells for GF180MCU provided by GlobalFoundries.☆18Dec 5, 2022Updated 3 years ago
- Project aimed at implementing floating point operators using the DSP48E1 slice.☆29Mar 29, 2013Updated 13 years ago
- Hardware transactions library for Amaranth☆26May 14, 2026Updated last week
- ☆15Jan 25, 2026Updated 3 months ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Fabric generator and CAD tools graphical frontend☆18Aug 5, 2025Updated 9 months ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆76Updated this week
- A configurable RTL to bitstream FPGA toolchain☆61Apr 24, 2026Updated 3 weeks ago
- Alliance VLSI CAD Tools (LIP6)☆22Dec 11, 2025Updated 5 months ago
- LunaPnR is a place and router for integrated circuits☆47Feb 11, 2026Updated 3 months ago
- Ethernet-MAC System verilog☆12May 28, 2018Updated 7 years ago
- ☆16Oct 30, 2021Updated 4 years ago
- System on Chip toolkit for Amaranth HDL☆101Mar 3, 2026Updated 2 months ago
- PCIe GEN1, GEN2 and GEN3 Scrambler, This Scrambler is able to scramble 1,2 and 4 bytes of data in 1 clock cycle in respect to the scrambl…☆18Jul 5, 2025Updated 10 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Project 1.1 Simulate a Skywater 130nm standard cell using ngspice☆14Jul 18, 2025Updated 10 months ago
- Yosys plugin for logic locking and supply-chain security☆24Apr 5, 2025Updated last year
- Small footprint and configurable HyperBus core☆14Jul 6, 2022Updated 3 years ago
- ☆61Jul 11, 2025Updated 10 months ago
- Kogge-Stone Adder in Verilog☆16Nov 19, 2021Updated 4 years ago
- An automatic clock gating utility☆53Apr 15, 2025Updated last year
- Open-source PDK version manager☆47Apr 23, 2026Updated 3 weeks ago
- Wameedh Scientific Club Deep Learning for Computer Vision workshop repository.☆12Apr 2, 2024Updated 2 years ago
- A Vivado IP package of the PicoRV32 RISC-V processor☆15Jul 9, 2020Updated 5 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Single Instruction Multiple Threads GPU Core with textbook Streaming Multi-Processor features☆65Jan 30, 2026Updated 3 months ago
- DisplayPort IP-core☆85May 8, 2026Updated last week
- ☆24Apr 12, 2026Updated last month
- Low level arithmetic primitives in RTL☆24Apr 3, 2020Updated 6 years ago
- Open source designs developed with IHP 130nm BiCMOS Open Source PDK. Documentation at https://ihp-open-ip.readthedocs.io/en/latest/☆68Apr 28, 2026Updated 3 weeks ago
- ☆15May 6, 2026Updated 2 weeks ago
- A configurable SRAM generator☆62Updated this week
- Introduction to Chip Design☆56Apr 21, 2026Updated last month
- FOSSi Foundation Website☆19Oct 5, 2024Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Greyhound on IHP SG13G2 0.13 μm BiCMOS process☆98May 10, 2026Updated last week
- Small footprint and configurable Inter-Chip communication cores☆66May 11, 2026Updated last week
- Open-source RTL logic simulator with CUDA acceleration☆274Sep 30, 2025Updated 7 months ago
- RTOS for embedded systems☆14Sep 19, 2024Updated last year
- A compact, configurable RISC-V core☆13Jul 31, 2025Updated 9 months ago
- Open-source implementations of reference Physical True Random Number Generators (TRNG or PTRNG) based on ring oscillators.☆17Mar 26, 2026Updated last month
- Gate-level visualization generator for SKY130-based chip designs.☆20Jul 22, 2021Updated 4 years ago