Alternatives and similar repositories for e-boost

Users that are interested in e-boost are comparing it to the libraries listed below

• Yu-Maryland / Gamora
  Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)
  ☆55Updated last year
• Gy-Hu / E-Syn
  E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)
  ☆41Updated last year
• Yu-Maryland / MapTune
  MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…
  ☆22Updated 9 months ago
• fangwenji / tacas23-wasim
  ☆13Updated 3 years ago
• cure-lab / DeepGate
  This is an official implementation for "DeepGate: Learning Neural Representations of Logic Gates".
  ☆24Updated 2 years ago
• amahzoon / genmul
  ☆19Updated 5 years ago
• hkustgz-zhang-lab / ABCPaperCheck
  Research paper based on or related to ABC.
  ☆70Updated 2 weeks ago
• cure-lab / DeepGate2
  ☆16Updated 2 years ago
• ckchengucsd / SMTCellUCSD
  Cell Layout Generation for DTCO/STCO Exploration Toolkit
  ☆21Updated 8 months ago
• HybridCEC / Hybrid-CEC
  A high-efficiency hybrid solving CEC algorithm
  ☆14Updated 2 years ago
• cornell-zhang / HOGA
  Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits
  ☆35Updated last year
• OSCC-Project / iMap
  Logic optimization and technology mapping tool.
  ☆20Updated 2 years ago
• yaoxufeng / RTLRewriter-Bench
  ☆44Updated last year
• cornell-zhang / eqmap
  Using e-graphs for logic synthesis (ICCAD'25)
  ☆31Updated this week
• hkust-zhiyao / CircuitFusion
  CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)
  ☆32Updated 9 months ago
• cuhk-eda / CULS
  GPU-based logic synthesis tool
  ☆97Updated 2 months ago
• Entropy-xcy / sns
  ☆20Updated 3 years ago
• zshi0616 / DeepGate2
  ☆31Updated 2 years ago
• Yu-Maryland / Verilog-to-PyG
  ☆30Updated last year
• zshi0616 / python-deepgate
  ☆27Updated last year
• arminbiere / aiger
  AIGER And-Inverter-Graph Library
  ☆97Updated 3 weeks ago
• laiyao1 / ArithTreeRL
  The release for paper "Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs"
  ☆14Updated last year
• Gy-Hu / HWMCC24-benchmark
  Collection for submission (Hardware Model Checking Benchmark)
  ☆13Updated 2 months ago
• hkust-zhiyao / AssertLLM
  Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
  ☆49Updated last year
• lydiawunan / LOSTIN
  LOSTIN: Logic Optimization via Spatio-Temporal Information with Hybrid Graph Models
  ☆26Updated 3 years ago
• SJTU-ECTL / GOMIL
  GOMIL: Global Optimization of Multiplier by Integer Linear Programming
  ☆13Updated 4 years ago
• alanminko / iwls2022-ls-contest
  Problems and Results of IWLS 2022 Programming Contest
  ☆21Updated 9 months ago
• lnis-uofu / ML-Mapper
  ☆13Updated 3 years ago
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆79Updated last month
• SJTU-ECTL / ALSRAC
  ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set
  ☆21Updated last year