Alternatives and similar repositories for LLMs-for-EDA-Tutorial

Users that are interested in LLMs-for-EDA-Tutorial are comparing it to the libraries listed below

• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆60Updated 7 months ago
• Yu-Maryland / Verilog-to-PyG
  ☆29Updated last year
• HKUSTGZ-MICS-LYU / FlattenRTL
  This is a python repo for flattening Verilog
  ☆20Updated last week
• Yu-Maryland / Gamora
  Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)
  ☆55Updated 11 months ago
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆74Updated 3 weeks ago
• IntelLabs / FloorSet
  ☆77Updated last week
• NVlabs / CircuitOps
  ☆95Updated 6 months ago
• scale-lab / BACS
  Benchmarks for Approximate Circuit Synthesis
  ☆17Updated 5 years ago
• Entropy-xcy / sns
  ☆20Updated 3 years ago
• pku-dasys / easymac
  ☆16Updated 3 years ago
• cuhk-eda / CULS
  GPU-based logic synthesis tool
  ☆97Updated last month
• rachelselinar / DREAMPlaceFPGA
  An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit
  ☆91Updated 7 months ago
• TILOS-AI-Institute / MLCAD-2023-FPGA-Macro-Placement-Contest
  ☆32Updated 2 years ago
• ASU-VDA-Lab / ASP-DAC24-Tutorial
  This GitHub repo is for the OpenROAD and CircuitOps Tutorial at ASP-DAC 2024
  ☆53Updated 11 months ago
• lamda-bbo / Open3DBench
  Official implementation of paper "Open3DBench: Open-Source Benchmark for 3D-IC Backend Implementation and PPA Evaluation".
  ☆75Updated 6 months ago
• HKUST-GZ-VLSI / Design-Dataset
  This is a repo to store circuit design datasets
  ☆19Updated last year
• hkust-zhiyao / CircuitFusion
  CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)
  ☆30Updated 8 months ago
• zshi0616 / python-deepgate
  ☆26Updated last year
• ieee-ceda-datc / datc-rdf-Metrics4ML
  ☆32Updated 4 years ago
• hkust-zhiyao / RTLLM
  An open-source benchmark for generating design RTL with natural language
  ☆152Updated last year
• NVlabs / INSTA
  ☆90Updated 6 months ago
• lydiawunan / HLS-Perf-Prediction-with-GNNs
  High-Level Synthesis Performance Prediction using GNNs: Benchmarking, Modeling, and Advancing
  ☆53Updated last year
• UT-LCA / ML4Accel-Dataset
  Dataset for ML-guided Accelerator Design
  ☆43Updated last year
• zslwyuan / AMF-Placer
  AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…
  ☆109Updated last year
• tsung-wei-huang / ece5960-physical-design
  ☆41Updated 3 years ago
• yaoxufeng / RTLRewriter-Bench
  ☆42Updated last year
• UCLA-VAST / GNN-DSE
  DAC'22 paper: "Automated Accelerator Optimization Aided by Graph Neural Networks"
  ☆40Updated 2 years ago
• ASU-VDA-Lab / 2024_ICCAD_Contest_Gate_Sizing_Benchmark
  ☆24Updated last year
• NYU-MLDA / OpenABC
  OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph…
  ☆141Updated 5 months ago
• The-OpenROAD-Project / asap5
  ☆36Updated 2 years ago