Alternatives and similar repositories for LLMs-for-EDA-Tutorial

Users that are interested in LLMs-for-EDA-Tutorial are comparing it to the libraries listed below

• Yu-Maryland / Verilog-to-PyG
  ☆24Updated last year
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆48Updated last week
• TILOS-AI-Institute / MLCAD-2023-FPGA-Macro-Placement-Contest
  ☆29Updated last year
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆59Updated 3 weeks ago
• ieee-ceda-datc / datc-rdf-Metrics4ML
  ☆31Updated 3 years ago
• bu-icsg / TAP-2.5D
  ☆33Updated 4 years ago
• ASU-VDA-Lab / ASP-DAC24-Tutorial
  This GitHub repo is for the OpenROAD and CircuitOps Tutorial at ASP-DAC 2024
  ☆48Updated 4 months ago
• Entropy-xcy / sns
  ☆17Updated 2 years ago
• cuhk-eda / CULS
  GPU-based logic synthesis tool
  ☆81Updated 10 months ago
• scale-lab / BACS
  Benchmarks for Approximate Circuit Synthesis
  ☆16Updated 4 years ago
• Yu-Maryland / Gamora
  Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)
  ☆50Updated 4 months ago
• ASU-VDA-Lab / 2024_ICCAD_Contest_Gate_Sizing_Benchmark
  ☆23Updated 6 months ago
• NVlabs / CircuitOps
  ☆80Updated 2 months ago
• laiyao1 / ArithTreeRL
  The release for paper "Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs"
  ☆13Updated 8 months ago
• zshi0616 / python-deepgate
  ☆22Updated 11 months ago
• IntelLabs / FloorSet
  ☆72Updated 5 months ago
• lamda-bbo / Efficient-TDP
  Official implementation of DATE'25 paper "Timing-Driven Global Placement by Efficient Critical Path Extraction".
  ☆44Updated 3 weeks ago
• krzhu / abcRL
  MLCAD 2020: Reinforcement for logic optimization sequence exploration
  ☆28Updated 4 years ago
• scale-lab / OpenPhySyn
  EDA physical synthesis optimization kit
  ☆57Updated last year
• pku-dasys / easymac
  ☆16Updated 3 years ago
• HKUSTGZ-MICS-LYU / FlattenRTL
  This is a python repo for flattening Verilog
  ☆16Updated 3 weeks ago
• zslwyuan / AutoCellLibX
  AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining
  ☆15Updated 2 years ago
• MIRALab-USTC / ChiPBench
  ChiPBench:Benchmarking End-to-End Performance of AI-based Chip Placement Algorithms
  ☆39Updated last month
• NVlabs / GEM
  Open-source RTL logic simulator with CUDA acceleration
  ☆19Updated last week
• laiyao1 / AnalogCoder
  ☆57Updated 2 months ago
• RIOSLaboratory / Open3DFlow
  An open-source 3D IC design platform that leverages existing open EDA tools while incorporating tailored abstractions and customizations …
  ☆28Updated this week
• CODA-Team / AnalogGym
  ☆44Updated this week
• UCLA-VAST / GNN-DSE
  DAC'22 paper: "Automated Accelerator Optimization Aided by Graph Neural Networks"
  ☆40Updated last year
• rachelselinar / DREAMPlaceFPGA
  An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit
  ☆82Updated last month
• ABKGroup / TritonPart
  The first version of TritonPart
  ☆26Updated last year