☆17Apr 16, 2024Updated 2 years ago
Alternatives and similar repositories for rl-explorer
Users that are interested in rl-explorer are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- [DAC2024] Explainable Fuzzy Neural Network with Multi-Fidelity Reinforcement Learning for Micro-Architecture Design Space Exploration☆10Oct 31, 2024Updated last year
- ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis☆33Feb 20, 2024Updated 2 years ago
- PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions☆18Dec 18, 2023Updated 2 years ago
- The open-sourced version of BOOM-Explorer☆50May 31, 2023Updated 2 years ago
- ☆13Jan 20, 2023Updated 3 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization☆44May 29, 2025Updated 11 months ago
- ☆30Oct 24, 2016Updated 9 years ago
- This is a repo to store circuit design datasets☆19Jan 17, 2024Updated 2 years ago
- Seal5 - Semi-automated LLVM Support for RISC-V Extensions including Autovectorization☆26Mar 29, 2026Updated last month
- This is a python repo for flattening Verilog☆20Dec 19, 2025Updated 4 months ago
- Interactive evolutionary exploration of generative design spaces with large language models☆18Jun 26, 2024Updated last year
- ☆11Aug 4, 2022Updated 3 years ago
- ☆32Oct 7, 2022Updated 3 years ago
- Open source version of ArchGym project.☆130Apr 13, 2025Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆71May 29, 2025Updated 11 months ago
- CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)☆37Apr 13, 2025Updated last year
- ☆29Dec 24, 2023Updated 2 years ago
- 🐆 A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration for *AdderNet*☆21May 27, 2024Updated last year
- ☆29Jun 25, 2024Updated last year
- RISC-V Formal in Chisel☆13Apr 9, 2024Updated 2 years ago
- A Fast DNN Accelerator Design Space Exploration Framework.☆46Aug 10, 2022Updated 3 years ago
- Boosted E-Graph Extraction with Adaptive Heuristics and Exact Solving☆30Jan 7, 2026Updated 3 months ago
- 第一届 RISC-V 中国峰会的幻灯片等资料存放☆38Nov 17, 2022Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Research about dataflow architecture☆12Nov 30, 2023Updated 2 years ago
- ☆10Dec 17, 2025Updated 4 months ago
- ChatEDA: A Large Language Model Powered Autonomous Agent for EDA (TCAD'24, NAACL'25)☆51May 21, 2025Updated 11 months ago
- Collection for submission (Hardware Model Checking Benchmark)☆13Nov 9, 2025Updated 5 months ago
- SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model☆16Jan 29, 2024Updated 2 years ago
- HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators☆191Updated this week
- ☆20Nov 3, 2025Updated 5 months ago
- A DAG processor and compiler for a tree-based spatial datapath.☆16Aug 24, 2022Updated 3 years ago
- gem5 FS模式实验手册☆46Mar 8, 2023Updated 3 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration☆48May 21, 2022Updated 3 years ago
- A comprehensive, modular learning path for mastering UVM (Universal Verification Methodology) and pyuvm (Python UVM implementation) with …☆31Jan 25, 2026Updated 3 months ago
- A Formal Verification Framework for Chisel☆19Apr 9, 2024Updated 2 years ago
- ☆16May 20, 2019Updated 6 years ago
- PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions☆11Dec 18, 2023Updated 2 years ago
- Memory latency test☆13May 14, 2024Updated last year
- 我设计了一些数字集成电路的教学实验,供大家学习~☆38Jan 23, 2025Updated last year