baichen318 / rl-explorerLinks
☆15Updated last year
Alternatives and similar repositories for rl-explorer
Users that are interested in rl-explorer are comparing it to the libraries listed below
Sorting:
- The open-sourced version of BOOM-Explorer☆46Updated 2 years ago
- ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis☆33Updated last year
- ☆16Updated 3 years ago
- ☆32Updated last year
- ☆60Updated 8 months ago
- An integrated CGRA design framework☆91Updated 9 months ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆73Updated 8 months ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆83Updated 2 years ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆73Updated last year
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆64Updated last year
- This is a repo to store circuit design datasets☆19Updated last year
- A reference implementation of the Mind Mappings Framework.☆30Updated 4 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 4 years ago
- PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions☆17Updated 2 years ago
- A RISC-V BOOM Microarchitecture Power Modeling Framework☆30Updated 2 years ago
- ☆42Updated last year
- Dataset for ML-guided Accelerator Design☆42Updated last year
- A toolchain for rapid design space exploration of chiplet architectures☆68Updated 4 months ago
- A simulator for SK hynix AiM PIM architecture based on Ramulator 2.0☆49Updated 4 months ago
- The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…☆38Updated 4 months ago
- FSA: Fusing FlashAttention within a Single Systolic Array☆70Updated 4 months ago
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆66Updated last week
- A list of our chiplet simulaters☆44Updated 5 months ago
- ☆14Updated last month
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆83Updated 4 years ago
- ☆51Updated 3 weeks ago
- This repository contains the code for this paper: Chiplet-Gym: An RL-based Optimization Framework for Chiplet-based AI Accelerator☆21Updated last year
- agile hardware-software co-design☆52Updated 4 years ago
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆59Updated 6 months ago
- ☆50Updated 6 months ago