baichen318 / rl-explorerLinks
☆17Updated last year
Alternatives and similar repositories for rl-explorer
Users that are interested in rl-explorer are comparing it to the libraries listed below
Sorting:
- The open-sourced version of BOOM-Explorer☆45Updated 2 years ago
- ☆18Updated 4 years ago
- ☆62Updated 10 months ago
- ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis☆33Updated last year
- Dataset for ML-guided Accelerator Design☆43Updated last year
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆85Updated 2 years ago
- An integrated CGRA design framework☆91Updated 10 months ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆73Updated last month
- A list of our chiplet simulaters☆48Updated 7 months ago
- ☆33Updated last year
- PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions☆17Updated 2 years ago
- A toolchain for rapid design space exploration of chiplet architectures☆72Updated 6 months ago
- Template-based Reconfigurable Architecture Modeling Framework☆14Updated 3 years ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆75Updated last year
- [DATE 2022] PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs☆20Updated 3 years ago
- ☆42Updated last year
- A reference implementation of the Mind Mappings Framework.☆30Updated 4 years ago
- Artifact evaluation of PLDI'24 paper "Allo: A Programming Model for Composable Accelerator Design"☆33Updated last year
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆66Updated 8 months ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆67Updated 4 years ago
- This repository contains the code for this paper: Chiplet-Gym: An RL-based Optimization Framework for Chiplet-based AI Accelerator☆23Updated last year
- ☆55Updated 8 months ago
- DATE'24 paper: "Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs"☆19Updated last year
- ☆109Updated last year
- Release of stream-specialization software/hardware stack.☆121Updated 2 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- Zeonica is a simulator for CGRA and Wafer-Scale Accelerators.☆18Updated this week
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆65Updated last year
- A RISC-V BOOM Microarchitecture Power Modeling Framework☆31Updated 2 years ago
- CGRA Compilation Framework☆91Updated 2 years ago