daitoto / EDA-wiki
EDA wiki
☆53Updated 2 years ago
Alternatives and similar repositories for EDA-wiki
Users that are interested in EDA-wiki are comparing it to the libraries listed below
Sorting:
- An infrastructure for integrated EDA☆39Updated last year
- OpenDesign Flow Database☆16Updated 6 years ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆33Updated 2 months ago
- ☆105Updated 5 years ago
- Open source process design kit for 28nm open process☆55Updated last year
- ☆27Updated 7 years ago
- EDA physical synthesis optimization kit☆54Updated last year
- Collection of digital hardware modules & projects (benchmarks)☆55Updated last week
- DATC Robust Design Flow.☆37Updated 5 years ago
- ☆33Updated 5 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆41Updated 2 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆53Updated 3 years ago
- A hardware synthesis framework with multi-level paradigm☆38Updated 4 months ago
- A configurable SRAM generator☆48Updated 4 months ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- ☆71Updated 5 months ago
- ☆40Updated 3 months ago
- AMC: Asynchronous Memory Compiler☆48Updated 4 years ago
- ☆44Updated 5 years ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆37Updated 2 years ago
- This is a python repo for flattening Verilog☆16Updated last month
- OpenPiton Design Benchmark☆25Updated 2 years ago
- A LEF/DEF Utility.☆28Updated 5 years ago
- An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization☆30Updated last year
- A custom C++ routine to identify logic gates in the layout extracted netlist (SPICE) of digital circuits and generate gate-level Verilog …☆29Updated 8 months ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 4 years ago
- SKY130 SRAM macros generated by SRAM 22☆16Updated 3 weeks ago
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆81Updated 2 weeks ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆106Updated last year
- The ANUBIS benchmark suite for Incremental Synthesis☆12Updated 4 years ago