An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization
☆33Nov 13, 2023Updated 2 years ago
Alternatives and similar repositories for BLASYS
Users that are interested in BLASYS are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ABACUS is a tool for approximate logic synthesis☆14Jul 13, 2020Updated 5 years ago
- Benchmarks for Approximate Circuit Synthesis☆17Aug 2, 2020Updated 5 years ago
- ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set☆21Dec 23, 2024Updated last year
- A copy of the latest version of MVSIS☆13Apr 18, 2021Updated 5 years ago
- C++ truth table library☆66Jul 30, 2025Updated 9 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆13Dec 31, 2022Updated 3 years ago
- ☆21Nov 18, 2022Updated 3 years ago
- Chisel Project for Integrating RTL code into SDAccel☆17Jan 12, 2018Updated 8 years ago
- Generate versal system design from ONNX model. AI engine kernels. Sub-microsecond speeds for autoencoders.☆17Dec 29, 2024Updated last year
- Semi-Tenser Product based SAT and AllSAT solver, where it can solve CNF and circuit input.☆17Aug 2, 2023Updated 2 years ago
- MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…☆27Apr 9, 2025Updated last year
- Showcase examples for EPFL logic synthesis libraries☆205Apr 5, 2024Updated 2 years ago
- An advanced header-only exact synthesis library☆31Nov 24, 2022Updated 3 years ago
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆42Jul 17, 2024Updated last year
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- C++ header-only reasoning library☆17Jul 11, 2024Updated last year
- SmartNIC☆14Dec 13, 2018Updated 7 years ago
- SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis for PROBE 2.0☆19Jul 22, 2020Updated 5 years ago
- An advanced circuit-based sat solver☆37Feb 24, 2025Updated last year
- DATC RDF☆49Jul 31, 2020Updated 5 years ago
- Generator of arithmetic circuits (multipliers, adders) and approximate circuits☆41Aug 15, 2025Updated 8 months ago
- IDEA project source files☆112Apr 15, 2026Updated 2 weeks ago
- Gate-level timing estimation toolkit☆25Apr 11, 2022Updated 4 years ago
- DRiLLS: Deep Reinforcement Learning for Logic Synthesis Optimization (ASPDAC'20)☆118May 18, 2023Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- For Jar artifacts☆20Nov 8, 2025Updated 5 months ago
- An implementation of a BinaryConnect network for cifar10☆11Nov 4, 2019Updated 6 years ago
- Code for L0-ARM: Network Sparsification via Stochastic Binary Optimization☆15Oct 25, 2019Updated 6 years ago
- EPFL logic synthesis benchmarks☆244Mar 3, 2026Updated last month
- Fast Emulation of Approximate DNN Accelerators in PyTorch☆29Feb 23, 2024Updated 2 years ago
- A verilog parser☆19Apr 12, 2024Updated 2 years ago
- Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1☆21Nov 9, 2025Updated 5 months ago
- OpenTitan FI formal verification framework☆15Aug 29, 2023Updated 2 years ago
- ☆16Mar 2, 2021Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Designs for Process-Voltage-Temperature (PVT) Sensors with MCU☆24May 8, 2020Updated 5 years ago
- Collection of digital hardware modules & projects (benchmarks)☆96Feb 27, 2026Updated 2 months ago
- ☆12Sep 29, 2021Updated 4 years ago
- Generate an FPGA design for a TWN☆11Nov 4, 2019Updated 6 years ago
- muSYCL, the SYCL musical!☆13Aug 25, 2024Updated last year
- A logic synthesis tool☆88Apr 20, 2026Updated last week
- ☆59Jan 19, 2026Updated 3 months ago