NVlabs / verilog-evalLinks
Verilog evaluation benchmark for large language model
☆299Updated 3 weeks ago
Alternatives and similar repositories for verilog-eval
Users that are interested in verilog-eval are comparing it to the libraries listed below
Sorting:
- A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.☆215Updated 6 months ago
- An open-source benchmark for generating design RTL with natural language☆126Updated 9 months ago
- ☆179Updated 9 months ago
- ☆222Updated last year
- MAGE: A Multi-Agent Engine for Automated RTL Code Generation☆53Updated 3 months ago
- ☆47Updated 10 months ago
- ☆25Updated 3 months ago
- ☆50Updated 5 months ago
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆51Updated 2 months ago
- 🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit☆151Updated 3 months ago
- ☆70Updated 4 months ago
- OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph…☆130Updated 2 weeks ago
- ☆32Updated 5 months ago
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆257Updated last week
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆36Updated 9 months ago
- Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework (DAC 2024)☆45Updated 7 months ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆135Updated last month
- HLSyn benchmark for paper "Towards a Comprehensive Benchmark for FPGA Targeted High-Level Synthesis"☆29Updated last year
- ☆88Updated last month
- ☆179Updated 4 months ago
- ☆60Updated last week
- ☆271Updated 4 years ago
- Research and Materials on Hardware implementation of Transformer Model☆275Updated 5 months ago
- ☆147Updated 2 years ago
- Macro Placement - benchmarks, evaluators, and reproducible results from leading methods in open source☆275Updated 2 months ago
- EPFL logic synthesis benchmarks☆203Updated 3 weeks ago
- A RISC-V BOOM Microarchitecture Power Modeling Framework☆27Updated 2 years ago
- ☆14Updated 11 months ago
- Official implementation of paper "Open3DBench: Open-Source Benchmark for 3D-IC Backend Implementation and PPA Evaluation".☆43Updated last month
- ☆23Updated 4 months ago