NVlabs / verilog-evalLinks
Verilog evaluation benchmark for large language model
☆331Updated 3 months ago
Alternatives and similar repositories for verilog-eval
Users that are interested in verilog-eval are comparing it to the libraries listed below
Sorting:
- A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.☆232Updated 8 months ago
- An open-source benchmark for generating design RTL with natural language☆135Updated 11 months ago
- ☆186Updated last year
- ☆245Updated last year
- MAGE: A Multi-Agent Engine for Automated RTL Code Generation☆67Updated 6 months ago
- ☆30Updated 6 months ago
- ☆91Updated last week
- ☆74Updated 7 months ago
- ☆49Updated last year
- OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph…☆136Updated 3 months ago
- 🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit☆159Updated 6 months ago
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆58Updated 5 months ago
- ☆14Updated last year
- Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework (DAC 2024)☆50Updated 10 months ago
- ☆38Updated 7 months ago
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆271Updated 2 weeks ago
- ☆91Updated 4 months ago
- ☆201Updated 7 months ago
- ☆150Updated 2 years ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆140Updated 4 months ago
- ☆88Updated 2 months ago
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆39Updated last year
- A RISC-V BOOM Microarchitecture Power Modeling Framework☆30Updated 2 years ago
- ☆54Updated 5 months ago
- RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects - IEEE LAD'24☆23Updated last year
- A Chisel RTL generator for network-on-chip interconnects☆215Updated 2 months ago
- Official implementation of paper "Open3DBench: Open-Source Benchmark for 3D-IC Backend Implementation and PPA Evaluation".☆65Updated 4 months ago
- ☆275Updated 4 years ago
- Generative Benchmark for LLM-Aided Hardware Design☆23Updated 4 months ago
- Fix syntax errors of LLM-generated RTL☆39Updated last year