Verilog evaluation benchmark for large language model
☆378Jul 14, 2025Updated 7 months ago
Alternatives and similar repositories for verilog-eval
Users that are interested in verilog-eval are comparing it to the libraries listed below
Sorting:
- An open-source benchmark for generating design RTL with natural language☆162Nov 8, 2024Updated last year
- A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.☆255Feb 9, 2025Updated last year
- ☆201Oct 17, 2024Updated last year
- MAGE: A Multi-Agent Engine for Automated RTL Code Generation☆88Apr 11, 2025Updated 10 months ago
- LLM Evaluation Benchmark on Hardware Formal Verification☆37Apr 3, 2025Updated 11 months ago
- ☆44May 18, 2024Updated last year
- ☆265Jul 8, 2024Updated last year
- ☆17Nov 19, 2023Updated 2 years ago
- ☆99Jun 24, 2025Updated 8 months ago
- ☆117Mar 10, 2025Updated 11 months ago
- OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph…☆144Jul 23, 2025Updated 7 months ago
- ☆59Jan 19, 2026Updated last month
- SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model☆15Jan 29, 2024Updated 2 years ago
- ☆34Dec 21, 2025Updated 2 months ago
- RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects - IEEE LAD'24☆33Jun 5, 2024Updated last year
- Python-based Hardware Design Processing Toolkit for Verilog HDL☆773Jun 15, 2024Updated last year
- ☆55Oct 8, 2024Updated last year
- TuRTLe: A Unified Evaluation of LLMs for RTL Generation 🐢 (MLCAD 2025)☆39Feb 23, 2026Updated last week
- Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits☆35Aug 25, 2024Updated last year
- ☆33Aug 7, 2025Updated 6 months ago
- ☆30Apr 23, 2024Updated last year
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆58Jan 8, 2025Updated last year
- GPU-based logic synthesis tool☆100Nov 27, 2025Updated 3 months ago
- CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)☆33Apr 13, 2025Updated 10 months ago
- DeepIC3: Guiding IC3 Algorithms by Graph Neural Network Clause Prediction (ASP-DAC 2024)☆13Nov 2, 2023Updated 2 years ago
- ☆13Jan 20, 2023Updated 3 years ago
- ☆125Dec 5, 2025Updated 3 months ago
- high-performance RTL simulator☆186Jun 19, 2024Updated last year
- ☆54Sep 4, 2025Updated 6 months ago
- Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation (ICCAD 2024)☆37Jun 17, 2025Updated 8 months ago
- HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration☆15Sep 14, 2020Updated 5 years ago
- Random Generator of Btor2 Files☆10Sep 2, 2023Updated 2 years ago
- OriGen: Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection(ICCAD 2024)☆29Oct 20, 2024Updated last year
- Open-source RTL logic simulator with CUDA acceleration☆257Sep 30, 2025Updated 5 months ago
- An open-source EDA infrastructure and tools from netlist to GDS☆490Jan 10, 2026Updated last month
- ABC: System for Sequential Logic Synthesis and Formal Verification☆1,129Feb 27, 2026Updated last week
- LLM Evaluation Framework for Hardware Design Using Python-Embedded DSLs☆17Aug 26, 2024Updated last year
- This is a repo to store circuit design datasets☆19Jan 17, 2024Updated 2 years ago
- ☆19Nov 29, 2022Updated 3 years ago