wuhy68 / ChatEDAView external linksLinks
ChatEDA: A Large Language Model Powered Autonomous Agent for EDA (TCAD'24, NAACL'25)
☆42May 21, 2025Updated 8 months ago
Alternatives and similar repositories for ChatEDA
Users that are interested in ChatEDA are comparing it to the libraries listed below
Sorting:
- Datasets for EDA LLM research☆38Jan 17, 2025Updated last year
- ☆261Jul 8, 2024Updated last year
- [IJCAI 2024] QiMeng-CPU-v1: Automated CPU Design by Learning from Input-Output Examples☆27May 4, 2025Updated 9 months ago
- This is a repo to store circuit design datasets☆19Jan 17, 2024Updated 2 years ago
- Official implementation of DATE'25 paper "Timing-Driven Global Placement by Efficient Critical Path Extraction".☆62Jun 14, 2025Updated 8 months ago
- This is a python repo for flattening Verilog☆20Dec 19, 2025Updated last month
- ☆44May 18, 2024Updated last year
- ☆48Dec 10, 2024Updated last year
- The first large scale formally verified reasoning dataset for Verilog☆19May 16, 2025Updated 8 months ago
- Boosted E-Graph Extraction with Adaptive Heuristics and Exact Solving☆25Jan 7, 2026Updated last month
- ☆15Aug 8, 2024Updated last year
- ☆11Mar 3, 2025Updated 11 months ago
- OpenROAD Agent. This repository contain the model to train and testing the model using EDA Corpus dataset.☆21Jul 24, 2025Updated 6 months ago
- CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)☆33Apr 13, 2025Updated 10 months ago
- ☆17Apr 16, 2024Updated last year
- ☆53Sep 4, 2025Updated 5 months ago
- Cell Layout Generation for DTCO/STCO Exploration Toolkit☆22May 24, 2025Updated 8 months ago
- Agentic Benchmark for LLM-Crafted Heuristics in Combinatorial Optimization (ICLR'26)☆63Updated this week
- This is the Github Repo for the paper: MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis O…☆60Jul 29, 2025Updated 6 months ago
- LLM Evaluation Benchmark on Hardware Formal Verification☆35Apr 3, 2025Updated 10 months ago
- GOMIL: Global Optimization of Multiplier by Integer Linear Programming☆13Aug 25, 2021Updated 4 years ago
- Python version of tools to work with AIG formatted files☆12May 20, 2025Updated 8 months ago
- Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization☆41May 29, 2025Updated 8 months ago
- NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph (DAC'25)☆23Dec 21, 2025Updated last month
- ☆32Aug 7, 2025Updated 6 months ago
- ☆16Oct 9, 2025Updated 4 months ago
- LLM Agent for Hardware Description Language☆20Jun 7, 2025Updated 8 months ago
- LLM4HWDesign Starting Toolkit☆19Oct 4, 2024Updated last year
- An open-source EDA infrastructure and tools from netlist to GDS☆481Jan 10, 2026Updated last month
- ☆20Apr 9, 2025Updated 10 months ago
- ☆23Nov 25, 2024Updated last year
- Gate-level timing estimation toolkit☆25Apr 11, 2022Updated 3 years ago
- VLSI EDA Global Router☆80Jan 22, 2018Updated 8 years ago
- This repo awesome-AI4EDA contains the source for the webpage: https://ai4eda.github.io, which is a curated paper list of awesome AI for E…☆184Jun 15, 2025Updated 7 months ago
- Layout Symmetry Annotation for Analog Circuits with GraphNeural Networks☆16Apr 7, 2023Updated 2 years ago
- ☆18Feb 3, 2022Updated 4 years ago
- Artificial Netlist Generator☆46Mar 19, 2024Updated last year
- ☆125Jan 20, 2026Updated 3 weeks ago
- This repository hosts the information of SPICEPilot: a training free LLM data-augmentation, new bench marking and future road-map.☆26May 23, 2025Updated 8 months ago