☆25Nov 7, 2024Updated last year
Alternatives and similar repositories for 2024_ICCAD_Contest_Gate_Sizing_Benchmark
Users that are interested in 2024_ICCAD_Contest_Gate_Sizing_Benchmark are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆99Jun 24, 2025Updated 8 months ago
- ☆33Dec 16, 2021Updated 4 years ago
- This GitHub repo is for the OpenROAD and CircuitOps Tutorial at ASP-DAC 2024☆54Jan 19, 2025Updated last year
- ☆18Oct 9, 2025Updated 5 months ago
- Xplace 3.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability and Timing Optimization☆158Jan 16, 2026Updated 2 months ago
- ☆10Apr 8, 2025Updated 11 months ago
- AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining☆18Nov 1, 2022Updated 3 years ago
- This repo contains the code that runs RL+GNN to optimize LDOs in SKY130 process.☆48Jun 24, 2024Updated last year
- Implementation of hMETIS☆12Aug 2, 2022Updated 3 years ago
- ☆59Jan 19, 2026Updated 2 months ago
- Layout Symmetry Annotation for Analog Circuits with GraphNeural Networks☆16Apr 7, 2023Updated 2 years ago
- ☆20Jan 13, 2025Updated last year
- This is the repository of IPs of the group in USC who is developing Analog Mixed-signal Parameter Search Engine (AMPSE). You can download…☆25Mar 11, 2023Updated 3 years ago
- This is an official implementation for "DeepGate: Learning Neural Representations of Logic Gates".☆25Jul 12, 2023Updated 2 years ago
- ☆14Jun 12, 2024Updated last year
- DATC Robust Design Flow.☆35Jan 21, 2020Updated 6 years ago
- A circuit-element level explainer to explain machine learning model's prediction on chip layouts.☆18Oct 30, 2023Updated 2 years ago
- Problems and Results of IWLS 2022 Programming Contest☆22Apr 12, 2025Updated 11 months ago
- Datasets for EDA LLM research☆39Jan 17, 2025Updated last year
- ☆26Apr 24, 2021Updated 4 years ago
- Incremental Timing-Driven Placement, problem C of ICCAD contest 2015☆15Sep 28, 2017Updated 8 years ago
- Awesome machine learning for logic synthesis☆30Sep 21, 2022Updated 3 years ago
- Cell Layout Generation for DTCO/STCO Exploration Toolkit☆23May 24, 2025Updated 9 months ago
- repository for a bandgap voltage reference in SKY130 technology☆42Jan 20, 2023Updated 3 years ago
- This is the XDM netlist converter, used to convert PSPICE and HSPICE netists into Xyce format.☆22Feb 15, 2024Updated 2 years ago
- Collection of digital hardware modules & projects (benchmarks)☆85Feb 27, 2026Updated 3 weeks ago
- ☆13Jan 21, 2022Updated 4 years ago
- An open-source EDA infrastructure and tools from netlist to GDS☆491Mar 11, 2026Updated last week
- MLCAD 2020: Reinforcement for logic optimization sequence exploration☆29Oct 17, 2020Updated 5 years ago
- Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization☆43May 29, 2025Updated 9 months ago
- utilities for batched llm calls with retries☆49Updated this week
- Advanced Integrated Circuits 2024☆24Nov 16, 2024Updated last year
- awesome-Analog-IC-Design-Automation☆48Apr 19, 2023Updated 2 years ago
- discrete gate sizing☆14Nov 23, 2020Updated 5 years ago
- tools regarding on analog modeling, validation, and generation☆22Apr 11, 2023Updated 2 years ago
- 开发环境是Windows 10, Quartus。硬件开发语言是Verilog。 利用FPGA开发的智能小车，分为两个部分，控制器部分和小车部分，通过蓝牙信号进行连接。 控制部分可以通过加速度传感器检测手势，从而控制小车的前后左右。 加速度传感器还可以检测人体是否摔倒…☆13Mar 10, 2019Updated 7 years ago
- Design of Analog Blocks in Skywaters 130nm meeting corners: different flavors of OTA, BandGap, LDO.☆30Jul 30, 2022Updated 3 years ago
- A High-performance Timing Analysis Tool for VLSI Systems☆10Feb 11, 2021Updated 5 years ago
- GPU-based logic synthesis tool☆100Nov 27, 2025Updated 3 months ago