Alternatives and similar repositories for 2024_ICCAD_Contest_Gate_Sizing_Benchmark

Users that are interested in 2024_ICCAD_Contest_Gate_Sizing_Benchmark are comparing it to the libraries listed below

• NVlabs / CircuitOps
  ☆89Updated 2 months ago
• ASU-VDA-Lab / ASP-DAC24-Tutorial
  This GitHub repo is for the OpenROAD and CircuitOps Tutorial at ASP-DAC 2024
  ☆51Updated 7 months ago
• ieee-ceda-datc / datc-rdf-Metrics4ML
  ☆31Updated 3 years ago
• NYU-MLDA / OpenABC
  OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph…
  ☆130Updated last month
• NVlabs / INSTA
  ☆85Updated 2 months ago
• zslwyuan / AutoCellLibX
  AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining
  ☆15Updated 2 years ago
• CODA-Team / AnalogGym
  ☆53Updated 2 months ago
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆59Updated last month
• lamda-bbo / Efficient-TDP
  Official implementation of DATE'25 paper "Timing-Driven Global Placement by Efficient Critical Path Extraction".
  ☆48Updated 2 months ago
• TILOS-AI-Institute / MLCAD-2023-FPGA-Macro-Placement-Contest
  ☆31Updated last year
• lamda-bbo / Open3DBench
  Official implementation of paper "Open3DBench: Open-Source Benchmark for 3D-IC Backend Implementation and PPA Evaluation".
  ☆45Updated 2 months ago
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆51Updated 2 months ago
• santoshsmalagi / Benchmarks
  A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.
  ☆55Updated 7 months ago
• daeyeon22 / artificial_netlist_generator
  Artificial Netlist Generator
  ☆40Updated last year
• cuhk-eda / Xplace
  Xplace 3.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability and Timing Optimization
  ☆135Updated 2 months ago
• ABKGroup / PROBE3.0
  ☆45Updated last year
• cuhk-eda / cu-gr
  CUGR, VLSI Global Routing Tool Developed by CUHK
  ☆137Updated 2 years ago
• IntelLabs / FloorSet
  ☆74Updated 2 months ago
• ycchen218 / EDA-IRdrop-Prediction
  This is a deep-learning based model for Electronic Design Automation(EDA), predicting the IR drop location on the chip.
  ☆28Updated 2 years ago
• luckyrantanplan / nthu-route
  VLSI EDA Global Router
  ☆75Updated 7 years ago
• RsynTeam / rsyn-x
  Rsyn – An Extensible Physical Synthesis Framework
  ☆129Updated last year
• TimingPredict / TimingPredict
  Official open source repository for "A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction" (DAC 2022)
  ☆77Updated last year
• cuhk-eda / CULS
  GPU-based logic synthesis tool
  ☆90Updated 2 weeks ago
• Yu-Maryland / Verilog-to-PyG
  ☆24Updated last year
• parkerluxu / awesome-Analog-IC-Design-Automation
  awesome-Analog-IC-Design-Automation
  ☆39Updated 2 years ago
• limbo018 / Limbo
  Library for VLSI CAD Design Useful parsers and solvers' api are implemented.
  ☆175Updated 3 months ago
• PKU-IDEA / OpenPARF
  🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit
  ☆151Updated 4 months ago
• ieee-ceda-datc / RDF-2019
  DATC RDF
  ☆50Updated 5 years ago
• magical-eda / MAGICAL
  Machine Generated Analog IC Layout
  ☆248Updated last year
• geziangfinn / easyPlace
  Reimplementation of the VLSI placement algorithm: ePlace and ePlace-MS
  ☆48Updated 9 months ago