Thinklab-SJTU / Awesome-LLM4EDA

Related projects ⓘ

Alternatives and complementary repositories for Awesome-LLM4EDA

• Thinklab-SJTU / awesome-ai4eda
  Awesome Artificial Intelligence for Electronic Design Automation Papers.
  ☆141Updated 10 months ago
• ai4eda / awesome-AI4EDA
  This repo awesome-AI4EDA contains the source for the webpage: https://ai4eda.github.io, which is a curated paper list of awesome AI for E…
  ☆127Updated 4 months ago
• hkust-zhiyao / RTLLM
  An open-source benchmark for generating design RTL with natural language
  ☆68Updated this week
• NVlabs / verilog-eval
  Verilog evaluation benchmark for large language model
  ☆175Updated 2 months ago
• hkust-zhiyao / RTL-Coder
  A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.
  ☆127Updated 3 weeks ago
• NYU-MLDA / OpenABC
  OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph…
  ☆113Updated last month
• laiyao1 / AnalogCoder
  ☆20Updated last month
• laiyao1 / maskplace
  ☆56Updated last year
• shailja-thakur / VGen
  ☆117Updated 3 weeks ago
• hkust-zhiyao / APPLE
  A circuit-element level explainer to explain machine learning model's prediction on chip layouts.
  ☆17Updated last year
• krzhu / abcRL
  MLCAD 2020: Reinforcement for logic optimization sequence exploration
  ☆26Updated 4 years ago
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆35Updated last month
• NVlabs / CircuitOps
  ☆71Updated 3 weeks ago
• circuitnet / CircuitNet
  CircuitNet: An Open-Source Dataset for Machine Learning Applications in Electronic Design Automation (EDA)
  ☆305Updated 4 months ago
• thu-nics / awesome_ai4eda
  ☆259Updated 3 years ago
• JBlocklove / LLMs-for-EDA-Tutorial
  ☆44Updated last month
• MIRALab-USTC / ChiPBench
  ChiPBench:Benchmarking End-to-End Performance of AI-based Chip Placement Algorithms
  ☆18Updated last month
• krzhu / abc_py
  Simple Python interface for ABC
  ☆23Updated last year
• hkust-zhiyao / RTL-Timer
  Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization
  ☆17Updated 4 months ago
• PKU-IDEA / OpenPARF
  🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit
  ☆115Updated last month
• wuhy68 / ChatEDAv1
  ChatEDA: A Large Language Model Powered Autonomous Agent for EDA
  ☆16Updated 3 months ago
• zshi0616 / DeepGate2
  ☆27Updated 11 months ago
• DfX-NYUAD / GNN4IC
  Must-read papers on Graph Neural Networks (GNNs) for Integrated Circuits (ICs) design, security and reliability. This collection of paper…
  ☆39Updated last year
• Thinklab-SJTU / EDA-AI
  Implementations of DeepPlace, PRNet, HubRouter and PreRoutGNN.
  ☆204Updated last month
• zshi0616 / python-deepgate
  ☆21Updated 4 months ago
• cuhk-eda / Xplace
  Xplace 2.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability Optimization
  ☆97Updated 4 months ago
• TimingPredict / TimingPredict
  Official open source repository for "A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction" (DAC 2022)
  ☆63Updated 2 months ago
• ASU-VDA-Lab / 2024_ICCAD_Contest_Gate_Sizing_Benchmark
  ☆19Updated this week
• TILOS-AI-Institute / MLCAD-2023-FPGA-Macro-Placement-Contest
  ☆29Updated last year
• laiyao1 / chipformer
  The release for ICML 2023 paper
  ☆35Updated 4 months ago