SiliconSemantics / firrtlatorLinks
firrtlator is a FIRRTL C++ library
☆23Updated 8 years ago
Alternatives and similar repositories for firrtlator
Users that are interested in firrtlator are comparing it to the libraries listed below
Sorting:
- Reference Hardware Implementations of Bit Extract/Deposit Instructions☆25Updated 7 years ago
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆37Updated 4 years ago
- Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FP…☆56Updated 4 years ago
- Open source fpga project leveraging vtr CAD flow.☆26Updated 2 years ago
- A Verilog Synthesis Regression Test☆37Updated last year
- Verilog AST☆21Updated last year
- Formal semantics of BSV (Bluespec SystemVerilog), given as a Haskell Program and accompanying document☆18Updated 9 years ago
- An executable specification of the RISCV ISA in L3.☆42Updated 6 years ago
- Languages, Tools, and Techniques for Accelerator Design☆33Updated 3 years ago
- A fault-injection framework using Chisel and FIRRTL☆37Updated 3 months ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 4 years ago
- The Shang high-level synthesis framework☆120Updated 11 years ago
- The PE for the second generation CGRA (garnet).☆17Updated 3 months ago
- netlistDB - Intermediate format for digital hardware representation with graph database API☆31Updated 4 years ago
- A time-predictable processor for mixed-criticality systems☆59Updated 9 months ago
- RTLCheck☆22Updated 6 years ago
- ☆103Updated 3 years ago
- Reticle evaluation (PLDI 2021)☆12Updated 4 years ago
- ☆26Updated 2 years ago
- soap - Structural Optimisation of Arithmetic Programs