firrtlator is a FIRRTL C++ library
☆23Dec 15, 2016Updated 9 years ago
Alternatives and similar repositories for firrtlator
Users that are interested in firrtlator are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Open source fpga project leveraging vtr CAD flow.☆26Mar 4, 2023Updated 3 years ago
- ☆20Feb 9, 2020Updated 6 years ago
- A coverage library for Chisel designs☆11Mar 12, 2020Updated 6 years ago
- A scala based simulator for circuits described by a LoFirrtl file☆50Jan 12, 2023Updated 3 years ago
- 🕒 Static Timing Analysis diagram renderer☆13Dec 13, 2023Updated 2 years ago
- A High-performance Timing Analysis Tool for VLSI Systems☆10Feb 11, 2021Updated 5 years ago
- Design space for LLVM/Clang work☆45Jun 14, 2012Updated 13 years ago
- ☆13Feb 13, 2021Updated 5 years ago
- Provides dot visualizations of chisel/firrtl circuites☆13Mar 12, 2019Updated 7 years ago
- ☆105Jun 27, 2022Updated 3 years ago
- ☆13Sep 30, 2020Updated 5 years ago
- R package providing Asio C++ library header files☆14Nov 26, 2025Updated 3 months ago
- Block-diagram style digital logic visualizer☆23Sep 16, 2015Updated 10 years ago
- Formal specification of the Haskell Language Report☆32Mar 2, 2026Updated 3 weeks ago
- Original RISC-V 1.0 implementation. Not supported.☆42Oct 4, 2018Updated 7 years ago
- Chisel artifacts developed under IBM's involvement with the DARPA PERFECT program☆31Sep 17, 2025Updated 6 months ago
- PLEASE MOVE TO PAWSv2☆16Feb 2, 2022Updated 4 years ago
- Not Another Range Library☆39Mar 9, 2014Updated 12 years ago
- Chisel components for FPGA projects☆129Sep 19, 2023Updated 2 years ago
- Single, dual, quad, eight, and sixteen-shader GP-GPU-Compute engines, along with 32-bit SYMPL RISC CPU and Coarse-Grained Scheduler, in o…☆22Jan 2, 2019Updated 7 years ago
- A C++ Library for Hardware Design and Simulation☆15May 17, 2020Updated 5 years ago
- An executable specification of the RISCV ISA in L3.☆42Mar 1, 2019Updated 7 years ago
- FPGA config visualized. demo:☆20Mar 17, 2020Updated 6 years ago
- Artifact repository for paper Automatic Generation of High-Performance Quantized Machine Learning Kernels☆17Oct 13, 2020Updated 5 years ago
- Carrier for efabless Caravel chip used for Google/Skywater 130nm shuttle program.☆18Sep 24, 2021Updated 4 years ago
- Experimentation around 'emil-e/rapidcheck' by combining it with libFuzzer☆27Jan 9, 2018Updated 8 years ago
- Chisel/Firrtl execution engine☆155Aug 21, 2024Updated last year
- ☆11Mar 16, 2016Updated 10 years ago
- Tools based upon slang for language server purpose☆22Updated this week
- BFM Tester for Chisel HDL☆14Nov 27, 2021Updated 4 years ago
- A vector processor implemented in Chisel☆21Aug 3, 2014Updated 11 years ago
- Galois RISC-V ISA Formal Tools☆62Aug 12, 2025Updated 7 months ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆24Mar 13, 2026Updated last week
- Marginally better than redstone☆103Aug 12, 2020Updated 5 years ago
- Submission template for Tiny Tapeout 04☆17Jun 15, 2024Updated last year
- Advanced Debug Interface☆14Jan 23, 2025Updated last year
- ☆20Mar 3, 2026Updated 2 weeks ago
- A basic implementation of C++ Concepts in C++14 (CppCon 2016 Lightning Talks)☆37Dec 1, 2016Updated 9 years ago
- ☆88Updated this week