SiliconSemantics / firrtlatorLinks
firrtlator is a FIRRTL C++ library
☆23Updated 9 years ago
Alternatives and similar repositories for firrtlator
Users that are interested in firrtlator are comparing it to the libraries listed below
Sorting:
- Reference Hardware Implementations of Bit Extract/Deposit Instructions☆24Updated 8 years ago
- Open source fpga project leveraging vtr CAD flow.☆26Updated 2 years ago
- Formal semantics of BSV (Bluespec SystemVerilog), given as a Haskell Program and accompanying document☆18Updated 9 years ago
- Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FP…☆57Updated 5 years ago
- An executable specification of the RISCV ISA in L3.☆42Updated 6 years ago
- Verilog AST☆21Updated 2 years ago
- A Verilog Synthesis Regression Test☆37Updated 3 weeks ago
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆38Updated 4 years ago
- Reticle evaluation (PLDI 2021)☆12Updated 4 years ago
- Languages, Tools, and Techniques for Accelerator Design☆33Updated 4 years ago
- ☆30Updated 3 years ago
- netlistDB - Intermediate format for digital hardware representation with graph database API☆31Updated 4 years ago
- Block-diagram style digital logic visualizer☆23Updated 10 years ago
- RISC-V port to Parallella Board☆13Updated 9 years ago
- A scala based simulator for circuits described by a LoFirrtl file☆49Updated 3 years ago
- Libre Silicon Compiler☆22Updated 4 years ago
- Create auto-scheduled data-parallel pipelines in hardware with user-friendly Python☆13Updated 4 years ago
- The BERI and CHERI processor and hardware platform☆50Updated 8 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆35Updated 5 years ago
- The Shang high-level synthesis framework☆120Updated 11 years ago
- Iodine: Verifying Constant-Time Execution of Hardware☆15Updated 4 years ago
- RISC-V BSV Specification☆23Updated 6 years ago
- A formal spec of the RISC-V Instruction Set Architecture, written in Bluespec BSV (executable, synthesizable)☆20Updated 8 years ago
- Fluid Pipelines☆11Updated 7 years ago
- A time-predictable processor for mixed-criticality systems☆60Updated last year
- Collection of test cases for Yosys☆17Updated 4 years ago
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆101Updated 6 years ago
- Verilog FPGA Parts Library. Old Octavo soft-CPU project.☆76Updated 6 years ago
- ABC: System for Sequential Logic Synthesis and Formal Verification☆31Updated this week
- Useful utilities for BAR projects☆32Updated 2 years ago