Alternatives and similar repositories for rotfpga

Users that are interested in rotfpga are comparing it to the libraries listed below

• asicsforthemasses / LunaPnR
  LunaPnR is a place and router for integrated circuits
  ☆47Updated 4 months ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• dbhi / vboard
  Virtual development board for HDL design
  ☆42Updated 2 years ago
• stnolting / fpga_torture
  🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
  ☆31Updated 3 years ago
• wyvernSemi / usbModel
  USB virtual model in C++ for Verilog
  ☆32Updated last year
• hdl / constraints
  Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards
  ☆45Updated last week
• tmeissner / vhdl_verification
  Examples and design pattern for VHDL verification
  ☆15Updated 9 years ago
• fossi-foundation / wishbone
  Specification of the Wishbone SoC Interconnect Architecture
  ☆48Updated 3 years ago
• AL-255 / Project-Yatsuhashi-Chip1
  ☆38Updated 2 years ago
• b224hisl / rioschip
  ☆33Updated 3 years ago
• GuzTech / misato
  RISC-V Processor written in Amaranth HDL
  ☆39Updated 3 years ago
• chili-chips-ba / openCologne-PCIE
  The first-ever opensource RTL core for PCIE EndPoint. Without vendor-locked HMs for Data Link, Transaction, Application layers; With stan…
  ☆46Updated last week
• hdl / packages
  Repo to help explain the different options users have for packaging.
  ☆18Updated 3 years ago
• antmicro / verilator-uvm-example
  Example of how to use UVM with Verilator
  ☆27Updated last month
• asinghani / sky130-chip-vis
  Gate-level visualization generator for SKY130-based chip designs.
  ☆21Updated 4 years ago
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆50Updated 3 years ago
• tmeissner / cryptocores
  cryptography ip-cores in vhdl / verilog
  ☆41Updated 4 years ago
• colognechip / gatemate_ila
  The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …
  ☆58Updated 3 weeks ago
• bobbl / rudolv
  RISC-V processor
  ☆32Updated 3 years ago
• Open-Source-Hardware-Initiative / AES
  Open Source AES
  ☆31Updated last month
• clairexen / picorv
  PicoRV
  ☆43Updated 5 years ago
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆36Updated 2 years ago
• enjoy-digital / litex-acorn-baseboard
  LiteX development baseboards arround the SQRL Acorn.
  ☆72Updated 8 months ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆66Updated last month
• westonb / sky130-analog
  Analog and power building blocks for sky130 pdk
  ☆20Updated 4 years ago
• nobodywasishere / VHDLproc
  VHDLproc is a VHDL preprocessor
  ☆24Updated 3 years ago
• TUM-LIS / glip
  Generic Logic Interfacing Project
  ☆48Updated 5 years ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆69Updated 2 months ago
• efabless / caravel_mgmt_soc_litex
  https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/
  ☆28Updated 10 months ago
• tmeissner / libvhdl
  Library of reusable VHDL components
  ☆28Updated last year