htfab / rotfpgaLinks
A reconfigurable logic circuit made of identical rotatable tiles.
☆23Updated 4 years ago
Alternatives and similar repositories for rotfpga
Users that are interested in rotfpga are comparing it to the libraries listed below
Sorting:
- USB virtual model in C++ for Verilog☆32Updated last year
- Virtual development board for HDL design☆42Updated 2 years ago
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆32Updated 3 years ago
- A padring generator for ASICs☆25Updated 2 years ago
- LunaPnR is a place and router for integrated circuits☆47Updated 5 months ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆46Updated last week
- Small footprint and configurable Inter-Chip communication cores☆66Updated 2 months ago
- Examples and design pattern for VHDL verification☆15Updated 9 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆69Updated 3 weeks ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆58Updated 2 months ago
- The first-ever opensource RTL core for PCIE EndPoint. Without vendor-locked HMs for Data Link, Transaction, Application layers; With stan…☆52Updated last week
- PicoRV☆43Updated 5 years ago
- RISC-V processor☆32Updated 3 years ago
- A configurable USB 2.0 device core☆32Updated 5 years ago
- Example of how to use UVM with Verilator☆31Updated last month
- CologneChip GateMate FPGA Module: GMM-7550☆27Updated 2 months ago
- cocotb extension for nMigen☆17Updated 3 years ago
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆22Updated 2 years ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆53Updated 2 years ago
- RISC-V Processor written in Amaranth HDL☆39Updated 3 years ago
- a small simple slow serial FPGA core☆16Updated 4 years ago
- ☆38Updated 3 years ago
- ☆33Updated 3 years ago
- Gate-level visualization generator for SKY130-based chip designs.☆21Updated 4 years ago
- Using VexRiscv without installing Scala☆39Updated 4 years ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆111Updated 3 weeks ago
- Specification of the Wishbone SoC Interconnect Architecture☆49Updated 3 years ago
- Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7☆91Updated 6 months ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 3 years ago
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆82Updated 5 years ago