Alternatives and similar repositories for xilinx-docker-mac

Users that are interested in xilinx-docker-mac are comparing it to the libraries listed below

• StanfordVLSI / dragonphy2
  Open Source PHY v2
  ☆32Updated last year
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆42Updated 5 years ago
• FPGA-Research / eFPGA---RTL-to-GDS-with-SKY130
  This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk
  ☆38Updated 4 years ago
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆63Updated last month
• rahulk29 / sram22
  A configurable SRAM generator
  ☆56Updated 4 months ago
• sgherbst / pysvinst
  Python library for parsing module definitions and instantiations from SystemVerilog files
  ☆25Updated 4 years ago
• Nic30 / pyDigitalWaveTools
  Python library for operations with VCD and other digital wave files
  ☆53Updated last month
• pulp-platform / redundancy_cells
  SystemVerilog IPs and Modules for architectural redundancy designs.
  ☆16Updated last month
• Nic30 / hdlConvertorAst
  Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
  ☆41Updated last month
• openecos-projects / icsprout55-pdk
  55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd.
  ☆153Updated 2 weeks ago
• gauravtewari / python-to-verilog
  Generate a Verilog Source file and testbench file for a given Moore FSM
  ☆17Updated 13 years ago
• lnis-uofu / TIGFET-10nm-PDK
  An open source PDK using TIGFET 10nm devices.
  ☆54Updated 3 years ago
• ahegazy / vlsi-notes
  Digital IC design and vlsi notes
  ☆12Updated 5 years ago
• grebe / ofdm
  Chisel Things for OFDM
  ☆32Updated 5 years ago
• cambridgehackers / open-src-cvc
  Mirror of tachyon-da cvc Verilog simulator
  ☆48Updated 2 years ago
• verilator / example-systemverilog
  ☆40Updated last year
• erinadreno / list_of_Xilinx_FPGAs
  ☆38Updated 6 months ago
• V0XNIHILI / parametrizable-floating-point-verilog
  Educational verilog library that supports IEEE754 floating point arithmetic with a parametrizable mantissa and exponent
  ☆30Updated 9 months ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆30Updated last year
• ReuelReuben / vsdSRAM
  SRAM
  ☆22Updated 5 years ago
• oscc-ip / sdram
  An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …
  ☆21Updated 8 months ago
• Ams0x57 / Digital_Adders_Verilog
  32 Bit RippleCarry, CarrySkip, CarrySelect, CarryIncrement, Sklansky, Brent-Kung, Kogge-Stone and CarryLookahead adders with their intern…
  ☆27Updated 7 years ago
• thesourcerer8 / StdCellLib
  LibreSilicon's Standard Cell Library Generator
  ☆22Updated 2 months ago
• riscv-verification / riscvISACOV
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆33Updated last month
• adki / cosim_bfm_library
  HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI
  ☆36Updated last year
• shariethernet / RPHAX
  RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…
  ☆21Updated 2 years ago
• freechipsproject / chisel-cheatsheet
  Chisel Cheatsheet
  ☆34Updated 2 years ago
• mohamed / fsm2sv
  SystemVerilog FSM generator
  ☆33Updated last year
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆48Updated 3 years ago
• JacoboJin / RISCV-on-PYNQ-Z2
  This repo is to inplemente the riscv soc on the xilinx pynq-z2 board
  ☆12Updated 2 years ago