IBM / hdl-toolsLinks
Facilitates building open source tools for working with hardware description languages (HDLs)
☆66Updated 6 years ago
Alternatives and similar repositories for hdl-tools
Users that are interested in hdl-tools are comparing it to the libraries listed below
Sorting:
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆127Updated 6 months ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆88Updated 4 years ago
- SpinalHDL Hardware Math Library☆94Updated last year
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆122Updated 4 years ago
- pulp_soc is the core building component of PULP based SoCs☆82Updated 11 months ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆80Updated this week
- A SystemVerilog source file pickler.☆60Updated last year
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 4 years ago
- For contributions of Chisel IP to the chisel community.☆70Updated last year
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆69Updated 11 months ago
- RISCV model for Verilator/FPGA targets☆53Updated 6 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- ☆40Updated 2 years ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆148Updated last week
- FPGA tool performance profiling☆105Updated last year
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆81Updated last month
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆120Updated 2 years ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆77Updated 6 months ago
- A simple DDR3 memory controller☆61Updated 3 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆51Updated 10 years ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆164Updated 3 months ago
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆63Updated 4 years ago
- FuseSoC standard core library☆151Updated 2 months ago
- RISC-V System on Chip Template☆160Updated 5 months ago
- RISC-V Nox core☆71Updated 6 months ago
- Xilinx Unisim Library in Verilog☆86Updated 5 years ago
- ideas and eda software for vlsi design☆51Updated last week
- Generic Register Interface (contains various adapters)☆135Updated 2 months ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆89Updated last year