Alternatives and similar repositories for hdl-tools

Users that are interested in hdl-tools are comparing it to the libraries listed below

• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated last year
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆88Updated 4 years ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆127Updated 6 months ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆60Updated last year
• tomverbeure / math
  SpinalHDL Hardware Math Library
  ☆94Updated last year
• verilator / example-systemverilog
  ☆40Updated 2 years ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆99Updated last year
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆151Updated last month
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆86Updated 5 years ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆148Updated 3 weeks ago
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆82Updated 10 months ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆69Updated 11 months ago
• antmicro / fastvdma
  Antmicro's fast, vendor-neutral DMA IP in Chisel
  ☆128Updated 8 months ago
• StanfordVLSI / dragonphy2
  Open Source PHY v2
  ☆33Updated last year
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆88Updated last year
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆122Updated 4 years ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆111Updated 3 weeks ago
• greenblat / vlsistuff
  ideas and eda software for vlsi design
  ☆51Updated 3 weeks ago
• aignacio / nox
  RISC-V Nox core
  ☆71Updated 6 months ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆44Updated 2 years ago
• SymbioticEDA / MARLANN
  Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks
  ☆91Updated 6 years ago
• efabless / sky130_sram_macros_old
  ☆38Updated 3 years ago
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆80Updated last year
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆163Updated 2 months ago
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆135Updated 2 months ago
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆80Updated 2 months ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆81Updated last month
• Nic30 / hwt
  VHDL/Verilog/SystemC code generator, simulator API written in python/c++
  ☆221Updated last month
• verilator / uvm
  Universal Verification Methodology (UVM) base libraries, with edits for Verilator
  ☆26Updated 3 months ago
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆105Updated last year