IBM / hdl-tools
Facilitates building open source tools for working with hardware description languages (HDLs)
☆63Updated 5 years ago
Alternatives and similar repositories for hdl-tools:
Users that are interested in hdl-tools are comparing it to the libraries listed below
- ☆38Updated last year
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆98Updated last month
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated 11 months ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆88Updated 5 years ago
- pulp_soc is the core building component of PULP based SoCs☆79Updated last month
- AXI Adapter(s) for RISC-V Atomic Operations☆62Updated this week
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆62Updated 11 months ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- Generic Register Interface (contains various adapters)☆116Updated 7 months ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆54Updated 3 months ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆83Updated 4 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated last year
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆65Updated 2 months ago
- Extensible FPGA control platform☆60Updated 2 years ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆45Updated 6 months ago
- FuseSoC standard core library☆134Updated last month
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 4 years ago
- Featherweight RISC-V implementation☆52Updated 3 years ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆33Updated 8 years ago
- FPGA tool performance profiling☆102Updated last year
- A SystemVerilog source file pickler.☆56Updated 6 months ago
- For contributions of Chisel IP to the chisel community.☆61Updated 6 months ago
- RISCV model for Verilator/FPGA targets☆51Updated 5 years ago
- ideas and eda software for vlsi design☆50Updated this week
- ☆39Updated 2 months ago
- ☆63Updated 6 years ago
- SpinalHDL Hardware Math Library☆85Updated 9 months ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆41Updated 2 years ago
- ☆78Updated last year
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆29Updated 9 months ago