Alternatives and similar repositories for verilog-lang

Users that are interested in verilog-lang are comparing it to the libraries listed below

• jiegec / chisel-memory-lower
  Lower chisel memories to SRAM macros
  ☆12Updated last year
• jiegec / rvv-kernels
  Implements kernels with RISC-V Vector
  ☆22Updated 2 years ago
• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆61Updated 3 years ago
• CircuitCoder / ChannelOS
  What if everything is a io_uring?
  ☆16Updated 3 years ago
• twd2 / fpga-nat64
  A four-10gbe-port dual-stack router with IPv4 and IPv6 translation support.
  ☆30Updated 5 years ago
• cyyself / cyyrv64
  My RV64 CPU (Work in progress)
  ☆19Updated 2 years ago
• jiegec / naiverouter
  A router IP written in Verilog.
  ☆12Updated 5 years ago
• thu-cs-lab / JieLabs-Web
  Backend & Frontend for JieLabs
  ☆22Updated 2 years ago
• dramforever / ixayoi
  (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog
  ☆12Updated 4 years ago
• jiegec / verilog-format
  A naive verilog/systemverilog formatter
  ☆21Updated 7 months ago
• CircuitCoder / mill
  RV32I by cats
  ☆15Updated 2 years ago
• dramforever / urvirt
  User-mode trap-and-emulate hypervisor for RISC-V
  ☆14Updated 3 years ago
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆30Updated 3 weeks ago
• jiegec / cpu
  Microarchitecture diagrams of several CPUs
  ☆43Updated last month
• char-fish-after-lunch / SystemOnCat
  An SoC with multiple RISC-V IMA processors.
  ☆19Updated 7 years ago
• dramforever / finlog
  Compiling finite generators to digital logic. WIP
  ☆13Updated 5 years ago
• riscv / riscv-control-transfer-records
  This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…
  ☆23Updated 8 months ago
• jiegec / fpu-wrappers
  Wrappers for open source FPU hardware implementations.
  ☆34Updated last year
• Oyami-Srk / RISCV-GDB-Paging
  Paging Debug tool for GDB using python
  ☆13Updated 3 years ago
• ljwljwljwljw / DiplomaticBackend
  ☆17Updated 3 years ago
• LainChip / LainCore
  Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.
  ☆45Updated last year
• jiegec / kb
  My knowledge base
  ☆72Updated last week
• z4yx / vivado-docker
  Dockerfile with Vivado for CI
  ☆27Updated 5 years ago
• chipsalliance / chisel-interface
  The 'missing header' for Chisel
  ☆21Updated 7 months ago
• trivialmips / linux-nontrivial-mips
  Linux porting to NonTrivialMIPS (based on linux-stable)
  ☆12Updated 6 years ago
• jiegec / jtag-remote-server
  Remote JTAG server for remote debugging
  ☆43Updated last year
• meow-chip / MeowRouter
  A hardware accelerated IP packet forwarder running on programmable ICs
  ☆15Updated 2 years ago
• chipsalliance / rocket-chip-fpga-shells
  Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards
  ☆20Updated 11 months ago
• dramforever / opensbi-h
  [No longer active] A fork of OpenSBI, with software-emulated hypervisor extension support
  ☆41Updated 2 months ago
• OpenRigil / openrigil-rtl
  Open-source RISC-V cryptographic hardware token, RTL repo
  ☆20Updated 3 years ago