jiegec / verilog-lang

Related projects ⓘ

Alternatives and complementary repositories for verilog-lang

• jiegec / chisel-memory-lower
  Lower chisel memories to SRAM macros
  ☆10Updated 7 months ago
• jiegec / rvv-kernels
  Implements kernels with RISC-V Vector
  ☆21Updated last year
• CircuitCoder / ChannelOS
  What if everything is a io_uring?
  ☆16Updated 2 years ago
• jiegec / cpu
  Microarchitecture diagrams of several CPUs
  ☆16Updated this week
• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆54Updated 2 years ago
• CircuitCoder / mill
  RV32I by cats
  ☆17Updated last year
• dramforever / ixayoi
  (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog
  ☆12Updated 3 years ago
• jiegec / naiverouter
  A router IP written in Verilog.
  ☆13Updated 4 years ago
• jiegec / fpu-wrappers
  Wrappers for open source FPU hardware implementations.
  ☆31Updated 6 months ago
• meow-chip / MeowRouter
  A hardware accelerated IP packet forwarder running on programmable ICs
  ☆15Updated last year
• ljwljwljwljw / DiplomaticBackend
  ☆17Updated 2 years ago
• jiegec / verilog-format
  A naive verilog/systemverilog formatter
  ☆20Updated 2 years ago
• char-fish-after-lunch / SystemOnCat
  An SoC with multiple RISC-V IMA processors.
  ☆19Updated 6 years ago
• thu-cs-lab / JieLabs-Web
  Backend & Frontend for JieLabs
  ☆22Updated last year
• twd2 / fpga-nat64
  A four-10gbe-port dual-stack router with IPv4 and IPv6 translation support.
  ☆31Updated 4 years ago
• jiegec / kb
  My knowledge base
  ☆38Updated last week
• riscv / riscv-control-transfer-records
  This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…
  ☆17Updated 2 weeks ago
• Harry-Chen / TrivialTomasulo
  Tomasulo Simulator written in React as the project for Computer Architecture course, Spring 2019, Tsinghua University
  ☆11Updated 5 years ago
• miaochenlu / learn_prefetcher
  hardware & software prefetcher
  ☆19Updated 10 months ago
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆27Updated 10 months ago
• dramforever / urvirt
  User-mode trap-and-emulate hypervisor for RISC-V
  ☆13Updated 2 years ago
• CircuitCoder / MeowRust
  Relaxed Rust (for cats)
  ☆16Updated 4 years ago
• circt / arc-tests
  A collection of tests and benchmarks for the Arc simulation backend of CIRCT
  ☆24Updated this week
• trivialmips / TrivialMIPS_Software
  Baremetal softwares for TrivialMIPS platform
  ☆10Updated 5 years ago
• CircuitCoder / MeoWave
  ☆10Updated last year
• wangrunji0408 / rjrouter
  [AFK] Hardware router in Chisel (THU Network Joint Lab 2020)
  ☆14Updated 4 years ago
• chipsalliance / chisel-interface
  The 'missing header' for Chisel
  ☆16Updated 3 weeks ago
• KireinaHoro / khtcp
  PKU CompNet'19 Lab 2 - Homebrew TCP
  ☆12Updated 4 years ago
• z4yx / vivado-docker
  Dockerfile with Vivado for CI
  ☆28Updated 4 years ago
• jiegec / cpu-micro-benchmarks
  CPU micro benchmarks
  ☆26Updated 3 months ago