jiegec / verilog-langLinks
A hand-written recursive decent Verilog parser.
☆11Updated 2 years ago
Alternatives and similar repositories for verilog-lang
Users that are interested in verilog-lang are comparing it to the libraries listed below
Sorting:
- Lower chisel memories to SRAM macros☆12Updated last year
- Implements kernels with RISC-V Vector☆22Updated 2 years ago
- What if everything is a io_uring?☆16Updated 2 years ago
- (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog☆12Updated 3 years ago
- Backend & Frontend for JieLabs☆22Updated 2 years ago
- A router IP written in Verilog.☆13Updated 5 years ago
- A naive verilog/systemverilog formatter☆21Updated 2 months ago
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆62Updated 3 years ago
- An SoC with multiple RISC-V IMA processors.☆19Updated 6 years ago
- RV32I by cats☆16Updated last year
- Wrappers for open source FPU hardware implementations.☆31Updated last year
- [AFK] Hardware router in Chisel (THU Network Joint Lab 2020)☆14Updated 4 years ago
- A hardware accelerated IP packet forwarder running on programmable ICs☆16Updated 2 years ago
- Microarchitecture diagrams of several CPUs☆36Updated last month
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆26Updated 4 months ago
- My RV64 CPU (Work in progress)☆19Updated 2 years ago
- Tex source for talk slide.☆10Updated 4 years ago
- ☆17Updated 3 years ago
- Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.☆41Updated 10 months ago
- ☆10Updated last year
- Dockerfile with Vivado for CI☆28Updated 5 years ago
- The 'missing header' for Chisel☆20Updated 2 months ago
- Tomasulo Simulator written in React as the project for Computer Architecture course, Spring 2019, Tsinghua University☆11Updated 5 years ago
- User-mode trap-and-emulate hypervisor for RISC-V☆13Updated 3 years ago
- Run SPEC CPU 2017 benchmark on OpenHarmony/HarmonyOS NEXT☆15Updated 4 months ago
- Toy ELF dynlinker & interp☆10Updated 11 months ago
- Warning: 🕳 ahead!☆16Updated 5 years ago
- A four-10gbe-port dual-stack router with IPv4 and IPv6 translation support.☆31Updated 5 years ago
- A Symmetric Multiprocessing OS Kernel over RISC-V☆31Updated 2 years ago
- This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…☆21Updated 3 months ago