jiegec / verilog-langLinks
A hand-written recursive decent Verilog parser.
☆11Updated 2 years ago
Alternatives and similar repositories for verilog-lang
Users that are interested in verilog-lang are comparing it to the libraries listed below
Sorting:
- Implements kernels with RISC-V Vector☆22Updated 2 years ago
- Lower chisel memories to SRAM macros☆12Updated last year
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆62Updated 3 years ago
- (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog☆12Updated 4 years ago
- My RV64 CPU (Work in progress)☆19Updated 2 years ago
- What if everything is a io_uring?☆16Updated 2 years ago
- A four-10gbe-port dual-stack router with IPv4 and IPv6 translation support.☆31Updated 5 years ago
- A router IP written in Verilog.☆13Updated 5 years ago
- Backend & Frontend for JieLabs☆22Updated 2 years ago
- A naive verilog/systemverilog formatter☆21Updated 5 months ago
- Dockerfile with Vivado for CI☆28Updated 5 years ago
- Microarchitecture diagrams of several CPUs☆39Updated 2 weeks ago
- User-mode trap-and-emulate hypervisor for RISC-V☆13Updated 3 years ago
- My knowledge base☆66Updated last month
- Paging Debug tool for GDB using python☆13Updated 3 years ago
- RV32I by cats☆16Updated 2 years ago
- Wrappers for open source FPU hardware implementations.☆33Updated last year
- Run Rocket Chip on VCU128☆30Updated 9 months ago
- ☆17Updated 3 years ago
- This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…☆23Updated 6 months ago
- Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.☆44Updated last year
- A hardware accelerated IP packet forwarder running on programmable ICs☆16Updated 2 years ago
- The 'missing header' for Chisel☆21Updated 5 months ago
- Compiling finite generators to digital logic. WIP☆14Updated 5 years ago
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆30Updated 3 weeks ago
- An SoC with multiple RISC-V IMA processors.☆19Updated 7 years ago
- Remote JTAG server for remote debugging☆40Updated last year
- [No longer active] A fork of OpenSBI, with software-emulated hypervisor extension support☆41Updated 3 weeks ago
- Tsinghua Advanced Networking Labs on FPGA☆38Updated 10 months ago
- Formal verification tools for Chisel and RISC-V☆13Updated last year