jiegec / verilog-lang
A hand-written recursive decent Verilog parser.
☆11Updated 2 years ago
Alternatives and similar repositories for verilog-lang:
Users that are interested in verilog-lang are comparing it to the libraries listed below
- Lower chisel memories to SRAM macros☆12Updated 10 months ago
- Implements kernels with RISC-V Vector☆21Updated last year
- (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog☆12Updated 3 years ago
- A router IP written in Verilog.☆13Updated 5 years ago
- Microarchitecture diagrams of several CPUs☆24Updated 2 weeks ago
- RV32I by cats☆17Updated last year
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆56Updated 2 years ago
- What if everything is a io_uring?☆16Updated 2 years ago
- Wrappers for open source FPU hardware implementations.☆30Updated 10 months ago
- Backend & Frontend for JieLabs☆22Updated last year
- A hardware accelerated IP packet forwarder running on programmable ICs☆16Updated 2 years ago
- ☆17Updated 2 years ago
- This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…☆19Updated last month
- Run Rocket Chip on VCU128☆29Updated 2 months ago
- Compiling finite generators to digital logic. WIP☆14Updated 4 years ago
- An SoC with multiple RISC-V IMA processors.☆19Updated 6 years ago
- A four-10gbe-port dual-stack router with IPv4 and IPv6 translation support.☆31Updated 4 years ago
- My RV64 CPU (Work in progress)☆19Updated 2 years ago
- Tex source for talk slide.☆10Updated 4 years ago
- My knowledge base☆42Updated this week
- Dockerfile with Vivado for CI☆28Updated 4 years ago
- The 'missing header' for Chisel☆18Updated 2 weeks ago
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆26Updated last month
- A naive verilog/systemverilog formatter☆20Updated 2 years ago
- Relaxed Rust (for cats)☆16Updated 5 years ago
- A Flexible Cache Architectural Simulator☆13Updated 2 months ago
- ☆10Updated last year
- User-mode trap-and-emulate hypervisor for RISC-V☆13Updated 3 years ago