schoeberl / lipsiLinks
Lipsi: Probably the Smallest Processor in the World
☆86Updated last year
Alternatives and similar repositories for lipsi
Users that are interested in lipsi are comparing it to the libraries listed below
Sorting:
- A Tiny Processor Core☆111Updated 2 months ago
- (System)Verilog to Chisel translator☆116Updated 3 years ago
- For contributions of Chisel IP to the chisel community.☆66Updated 10 months ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆177Updated 4 months ago
- An implementation of RISC-V☆43Updated last week
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- educational microarchitectures for risc-v isa☆67Updated 6 years ago
- 64-bit multicore Linux-capable RISC-V processor☆97Updated 5 months ago
- RISC-V Formal Verification Framework☆150Updated last week
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆147Updated last month
- RiscyOO: RISC-V Out-of-Order Processor☆162Updated 5 years ago
- Yet Another RISC-V Implementation☆97Updated last year
- Chisel components for FPGA projects☆126Updated 2 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆121Updated 2 months ago
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆101Updated 4 years ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- Provides dot visualizations of chisel/firrtl circuits☆121Updated 2 years ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆74Updated last year
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated 3 weeks ago
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆101Updated 5 years ago
- Facilitates building open source tools for working with hardware description languages (HDLs)☆65Updated 5 years ago
- Examples for creating AXI-interfaced peripherals in Chisel☆76Updated 9 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆57Updated 5 years ago
- Provides various testers for chisel users☆100Updated 2 years ago
- ☆108Updated last month
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆181Updated last week
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated 3 months ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆111Updated 2 years ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆118Updated this week
- SoftCPU/SoC engine-V☆54Updated 6 months ago