Alternatives and similar repositories for lipsi:

Users that are interested in lipsi are comparing it to the libraries listed below

• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆113Updated 2 years ago
• librecores / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆66Updated 6 years ago
• leros-dev / leros
  A Tiny Processor Core
  ☆108Updated last month
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆107Updated 3 years ago
• maltanar / fpga-tidbits
  Chisel components for FPGA projects
  ☆122Updated last year
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆141Updated 3 weeks ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆174Updated 9 months ago
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆62Updated 11 months ago
• csail-csg / riscy
  Riscy Processors - Open-Sourced RISC-V Processors
  ☆73Updated 6 years ago
• SpinalHDL / SpinalTemplateSbt
  A basic SpinalHDL project
  ☆84Updated last month
• Intensivate / learning-journey
  Chisel Learning Journey
  ☆109Updated 2 years ago
• maltanar / axi-in-chisel
  Examples for creating AXI-interfaced peripherals in Chisel
  ☆74Updated 9 years ago
• BSVLang / Main
  Main page
  ☆126Updated 5 years ago
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆136Updated this week
• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆74Updated 5 years ago
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆153Updated last week
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆156Updated 4 years ago
• csail-csg / pyverilator
  Python wrapper for verilator model
  ☆82Updated last year
• freechipsproject / chisel-testers
  Provides various testers for chisel users
  ☆100Updated 2 years ago
• SpinalHDL / SpinalWorkshop
  Labs to learn SpinalHDL
  ☆147Updated 10 months ago
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆148Updated 5 months ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆93Updated 7 months ago
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆97Updated 3 years ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆96Updated last month
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆51Updated 5 years ago
• freechipsproject / diagrammer
  Provides dot visualizations of chisel/firrtl circuits
  ☆119Updated 2 years ago
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆65Updated 9 months ago
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆83Updated 4 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated last month
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆61Updated 6 months ago