schoeberl / lipsiLinks
Lipsi: Probably the Smallest Processor in the World
☆86Updated last year
Alternatives and similar repositories for lipsi
Users that are interested in lipsi are comparing it to the libraries listed below
Sorting:
- A Tiny Processor Core☆110Updated 2 weeks ago
- (System)Verilog to Chisel translator☆115Updated 3 years ago
- educational microarchitectures for risc-v isa☆66Updated 6 years ago
- For contributions of Chisel IP to the chisel community.☆64Updated 8 months ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆178Updated 2 months ago
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆101Updated 3 years ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆117Updated 3 weeks ago
- Naive Educational RISC V processor☆85Updated 2 weeks ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆145Updated 2 months ago
- Yet Another RISC-V Implementation☆96Updated 10 months ago
- RiscyOO: RISC-V Out-of-Order Processor☆159Updated 5 years ago
- 64-bit multicore Linux-capable RISC-V processor☆93Updated 3 months ago
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆101Updated 5 years ago
- A RISC-V Core (RV32I) written in Chisel HDL☆103Updated 3 months ago
- RISC-V Formal Verification Framework☆143Updated this week
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆72Updated last year
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆113Updated this week
- Chisel Cheatsheet☆33Updated 2 years ago
- Basic floating-point components for RISC-V processors☆66Updated 5 years ago
- Chisel Learning Journey☆109Updated 2 years ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆229Updated 8 months ago
- An implementation of RISC-V☆38Updated 3 weeks ago
- Labs to learn SpinalHDL☆149Updated last year
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆168Updated this week
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆57Updated 5 years ago
- SoftCPU/SoC engine-V☆54Updated 4 months ago
- Provides dot visualizations of chisel/firrtl circuits☆120Updated 2 years ago
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆122Updated 2 months ago