jiegec / rocket-chip-vcu128
Run Rocket Chip on VCU128
☆30Updated 4 months ago
Alternatives and similar repositories for rocket-chip-vcu128:
Users that are interested in rocket-chip-vcu128 are comparing it to the libraries listed below
- ☆17Updated 3 years ago
- Implements kernels with RISC-V Vector☆22Updated 2 years ago
- ☆32Updated last week
- chipyard in mill :P☆77Updated last year
- ☆19Updated 3 years ago
- Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)☆55Updated last year
- The 'missing header' for Chisel☆18Updated last week
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated last year
- An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:☆14Updated last year
- RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Co…☆14Updated 11 months ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆51Updated 4 years ago
- Open-source non-blocking L2 cache☆38Updated this week
- A prototype GUI for chisel-development☆52Updated 4 years ago
- Wrappers for open source FPU hardware implementations.☆30Updated 11 months ago
- Chisel Cheatsheet☆33Updated last year
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆27Updated last month
- A bare-metal application to test specific features of the risc-v hypervisor extension☆37Updated last year
- The RTL source for AnyCore RISC-V☆32Updated 3 years ago
- ☆28Updated 3 months ago
- Open source high performance IEEE-754 floating unit☆67Updated last year
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆53Updated 4 years ago
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆60Updated 3 years ago
- upstream: https://github.com/RALC88/gem5☆31Updated last year
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆30Updated 10 months ago
- Spike with a coherence supported cache model☆13Updated 8 months ago
- ☆78Updated last year
- A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.☆27Updated 5 years ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆24Updated this week
- Workshop on Computer Architecture Research with RISC-V (CARRV)☆38Updated 4 months ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆32Updated last month