jiegec / rocket-chip-vcu128
Run Rocket Chip on VCU128
☆27Updated last week
Related projects ⓘ
Alternatives and complementary repositories for rocket-chip-vcu128
- ☆17Updated 2 years ago
- ☆31Updated last month
- Implements kernels with RISC-V Vector☆21Updated last year
- Open-source non-blocking L2 cache☆33Updated this week
- A prototype GUI for chisel-development☆52Updated 4 years ago
- chipyard in mill :P☆76Updated last year
- Wrappers for open source FPU hardware implementations.☆31Updated 7 months ago
- RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Co…☆14Updated 7 months ago
- Open source high performance IEEE-754 floating unit☆60Updated 8 months ago
- An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:☆12Updated 8 months ago
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆55Updated 2 years ago
- A bare-metal application to test specific features of the risc-v hypervisor extension☆35Updated 11 months ago
- ☆25Updated 10 months ago
- upstream: https://github.com/RALC88/gem5☆32Updated last year
- Setup scripts and files needed to compile CoreMark on RISC-V☆64Updated 4 months ago
- ☆75Updated 2 years ago
- Open-source high-performance non-blocking cache☆67Updated this week
- The RTL source for AnyCore RISC-V☆30Updated 2 years ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆27Updated 6 months ago
- This repo includes XiangShan's function units☆15Updated 2 weeks ago
- Unit tests generator for RVV 1.0☆63Updated last month
- ☆36Updated 9 months ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated 8 months ago
- The 'missing header' for Chisel☆16Updated last month
- A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.☆26Updated 4 years ago
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆25Updated last week
- sha256d mining chip written by chisel.☆28Updated 4 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆47Updated 2 years ago
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆57Updated last year
- ☆19Updated 2 years ago