maltanar / rosetta
Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ
☆33Updated 6 years ago
Alternatives and similar repositories for rosetta:
Users that are interested in rosetta are comparing it to the libraries listed below
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆40Updated 4 years ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆31Updated 7 months ago
- ☆42Updated 3 years ago
- This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…☆15Updated 5 years ago
- Open source fpga project leveraging vtr CAD flow.☆26Updated last year
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆23Updated 5 years ago
- CNN accelerator☆27Updated 7 years ago
- Implementation of the Advanced Encryption Standard in Chisel☆20Updated 2 years ago
- openHMC - an open source Hybrid Memory Cube Controller☆46Updated 8 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- ☆15Updated 3 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆39Updated last year
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 2 years ago
- Python interface to FPGA interchange format☆41Updated 2 years ago
- FGPU is a soft GPU architecture general purpose computing☆56Updated 4 years ago
- Reconfigurable Binary Engine☆15Updated 3 years ago
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- A collection of tools for working with Chisel-generated hardware in SystemC☆16Updated 5 years ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆26Updated 5 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆63Updated last week
- ☆20Updated 5 years ago
- Advanced Debug Interface☆13Updated 3 weeks ago
- IP-core package generator for AXI4/Avalon☆22Updated 6 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆20Updated last week
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆31Updated 3 months ago
- Adding PR to the PYNQ Overlay☆17Updated 7 years ago
- SoCRocket - Core Repository☆34Updated 7 years ago
- IPXACT packaging utilities for Chisel 3.x using Xilinx Vivado Design Suite.☆10Updated 6 years ago
- ☆36Updated 2 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 4 years ago