Alternatives and similar repositories for hazardflow

Users that are interested in hazardflow are comparing it to the libraries listed below

• kaist-cp / shakeflow
  ShakeFlow: Functional Hardware Description with Latency-Insensitive Interface Combinators (ASPLOS 2023)
  ☆54Updated 5 months ago
• kaist-cp / cs492-uarch
  ☆43Updated 7 months ago
• kaist-cp / memento
  Memento: A Framework for Detectable Recoverability in Persistent Memory (PLDI 2023)
  ☆16Updated 2 years ago
• casys-kaist / kev
  KAIST Educational Virtualization
  ☆15Updated 9 months ago
• apl-cornell / PDL
  A Hardware Pipeline Description Language
  ☆45Updated this week
• kaist-cp / kecc-public
  KECC: KAIST Educational C Compiler. IMPORTANT: DON'T FORK!
  ☆163Updated last month
• kaist-cp / rv6
  ☆131Updated 2 years ago
• vegaluisjose / reticle
  ☆40Updated 3 years ago
• mikeurbach / egg-netlist-synthesizer
  Using e-graphs to synthesize netlists from boolean logic.
  ☆14Updated last year
• vegaluisjose / vast
  Verilog AST
  ☆21Updated last year
• circt / arc-tests
  A collection of tests and benchmarks for the Arc simulation backend of CIRCT
  ☆29Updated 5 months ago
• Synthesys-Lab / assassyn
  Asynchronous semantics for architectural simulation and synthesis.
  ☆39Updated last week
• pku-liang / Hestia
  ☆17Updated 3 months ago
• agurfinkel / btor2mlir
  BTOR2 MLIR project
  ☆26Updated last year
• cucapra / dahlia
  Time-sensitive affine types for predictable hardware generation
  ☆145Updated last week
• mit-plv / koika
  A core language for rule-based hardware design 🦑
  ☆156Updated last month
• TeamVoss / VossII
  The source code to the Voss II Hardware Verification Suite
  ☆55Updated 3 weeks ago
• sequencer / zaozi
  A eDSL framework based on Scala and MLIR, focusing on the Hardware design.
  ☆39Updated this week
• uwplse / rake
  compiling DSLs to high-level hardware instructions
  ☆22Updated 2 years ago
• iscas-tis / ChiRVFormal
  Minimal RISC-V Chisel design strictly reflecting the ISA document for verification.
  ☆14Updated last month
• aqjune / mlir-tv
  A translation validation framework for MLIR
  ☆87Updated 3 months ago
• ucb-substrate / substrate2
  21st century electronic design automation tools, written in Rust.
  ☆31Updated last week
• IntelLabs / pycaliper
  PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…
  ☆22Updated last month
• gussmith23 / lakeroad
  FPGA synthesis tool powered by program synthesis
  ☆51Updated last week
• iscas-tis / CHA
  ☆19Updated last year
• mit-plv / hemiola
  A Coq framework to support structural design and proof of hardware cache-coherence protocols
  ☆14Updated 3 years ago
• agile-hw / lectures
  Lectures for the Agile Hardware Design course in Jupyter Notebooks
  ☆101Updated last month
• pku-liang / Cement
  The Next-gen Language & Compiler Powering Efficient Hardware Design
  ☆29Updated 6 months ago
• euphoric-hardware / rtl-simulation-reading
  ☆17Updated 3 weeks ago
• heterorefactor / heterorefactor
  HeteroRefactor: Refactoring for Heterogeneous Computing with FPGA
  ☆10Updated 3 years ago