sifive / block-pio-sifive
An example of on-boarding a PIO block in with duh and wake
☆12Updated 4 years ago
Related projects ⓘ
Alternatives and complementary repositories for block-pio-sifive
- A coverage library for Chisel designs☆11Updated 4 years ago
- Amazon F1-inspired Xilinx VCU118 hardware design framework☆10Updated 3 years ago
- A DMA Controller for RISCV CPUs☆14Updated 9 years ago
- A fault-injection framework using Chisel and FIRRTL☆34Updated last year
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆26Updated 5 years ago
- Useful utilities for BAR projects☆30Updated 10 months ago
- SCARV: a side-channel hardened RISC-V platform☆24Updated last year
- ☆13Updated 3 years ago
- Wake build descriptions of hardware generators☆12Updated 3 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 4 years ago
- Advanced Debug Interface☆12Updated last year
- Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores☆12Updated 3 months ago
- Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project☆17Updated last year
- A Rocket-based RISC-V superscalar in-order core☆28Updated 3 weeks ago
- Wavious DDR (WDDR) Physical interface (PHY) Software☆19Updated 2 years ago
- RTL blocks compatible with the Rocket Chip Generator☆14Updated 4 months ago
- This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…☆14Updated 5 years ago
- ☆21Updated 7 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆19Updated this week
- Chisel artifacts developed under IBM's involvement with the DARPA PERFECT program☆30Updated last year
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆52Updated 4 years ago
- ☆25Updated 4 years ago
- Wrapper for ETH Ariane Core☆19Updated 3 months ago
- Implementation of the Advanced Encryption Standard in Chisel☆20Updated 2 years ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆33Updated 6 years ago
- A Hardware Pipeline Description Language☆40Updated last year
- Chisel Cheatsheet☆31Updated last year
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆33Updated 4 years ago
- A Verilog Synthesis Regression Test☆34Updated 8 months ago