pku-liang / HestiaLinks
☆17Updated 8 months ago
Alternatives and similar repositories for Hestia
Users that are interested in Hestia are comparing it to the libraries listed below
Sorting:
- Using e-graphs for logic synthesis☆24Updated last month
- ☆50Updated 10 months ago
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆34Updated 10 months ago
- ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis☆34Updated last year
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆64Updated last year
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆52Updated 2 years ago
- Asynchronous semantics for architectural simulation and synthesis.☆57Updated last week
- ☆22Updated last month
- EQueue Dialect☆41Updated 3 years ago
- Parendi: Thousand-way Parallel RTL Simulation on the Graphcore IPU☆24Updated last week
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆43Updated 5 months ago
- A hardware synthesis framework with multi-level paradigm☆41Updated 10 months ago
- ☆18Updated 3 weeks ago
- GPGPU-Sim 中文注释版代码,包含 GPGPU-Sim 模拟器的最新版代码,经过中文注释,以帮助中文用户更好地理解和使用该模拟器。☆27Updated 11 months ago
- ☆61Updated 8 months ago
- A binary instrumentation tool to analyze load instructions in any off-the-shelf x86(-64) program. Described by Bera et al. in https://arx…☆23Updated last year
- Artifact evaluation of PLDI'24 paper "Allo: A Programming Model for Composable Accelerator Design"☆30Updated last year
- ☆21Updated 4 years ago
- Implementation of Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning in Chisel HDL. To know more, …☆17Updated 4 years ago
- ☆24Updated 5 years ago
- HeteroCL-MLIR dialect for accelerator design☆42Updated last year
- ☆16Updated 2 years ago
- A fast, accurate, and easy-to-integrate memory simulator that model memory system performance with bandwidth--latency curves.☆32Updated last month
- ☆17Updated 3 months ago
- ☆15Updated 3 years ago
- ☆40Updated 8 months ago
- Domain-Specific Architecture Generator 2☆21Updated 3 years ago
- ☆11Updated last year
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆80Updated last week
- ☆32Updated last year