pku-liang / HestiaLinks
☆17Updated 7 months ago
Alternatives and similar repositories for Hestia
Users that are interested in Hestia are comparing it to the libraries listed below
Sorting:
- ☆49Updated 9 months ago
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆32Updated 9 months ago
- ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis☆34Updated last year
- Parendi: Thousand-way Parallel RTL Simulation on the Graphcore IPU☆24Updated last year
- ☆18Updated 4 months ago
- Artifact evaluation of PLDI'24 paper "Allo: A Programming Model for Composable Accelerator Design"☆30Updated last year
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆43Updated 5 months ago
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆51Updated 2 years ago
- A hardware synthesis framework with multi-level paradigm☆41Updated 10 months ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆64Updated last year
- Domain-Specific Architecture Generator 2☆21Updated 3 years ago
- Implementation of Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning in Chisel HDL. To know more, …☆17Updated 4 years ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆44Updated 10 months ago
- ☆26Updated 2 years ago
- ☆36Updated 7 months ago
- EQueue Dialect☆40Updated 3 years ago
- ☆32Updated last year
- ☆24Updated 5 years ago
- A binary instrumentation tool to analyze load instructions in any off-the-shelf x86(-64) program. Described by Bera et al. in https://arx…☆23Updated last year
- GPGPU-Sim 中文注释版代码,包含 GPGPU-Sim 模拟器的最新版代码,经过中文注释,以帮助中文用户更好地理解和使用该模拟器。☆26Updated 10 months ago
- Virtualized Accelerator Orchestration for Multi-Tenant Workloads☆19Updated 11 months ago
- ☆60Updated 7 months ago
- ☆22Updated last week
- A unified simulation platform that combines hardware and software, enabling pre-silicon, full-stack, closed-loop evaluation of your robot…☆45Updated 7 months ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆78Updated last month
- HeteroCL-MLIR dialect for accelerator design☆41Updated last year
- CGRA framework with vectorization support.☆39Updated this week
- A DSL for Systolic Arrays☆82Updated 6 years ago
- Artifact for "DX100: A Programmable Data Access Accelerator for Indirection (ISCA 2025)" paper☆13Updated last week
- FSA: Fusing FlashAttention within a Single Systolic Array☆61Updated 3 months ago