lana555 / dynamaticLinks
☆87Updated last year
Alternatives and similar repositories for dynamatic
Users that are interested in dynamatic are comparing it to the libraries listed below
Sorting:
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- DASS HLS Compiler☆29Updated 2 years ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆74Updated 2 weeks ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆126Updated 2 years ago
- Next generation CGRA generator☆115Updated this week
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆160Updated 2 years ago
- ☆61Updated last week
- Benchmarks for Accelerator Design and Customized Architectures☆130Updated 5 years ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆138Updated 4 months ago
- ☆59Updated 2 years ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆127Updated 2 years ago
- An integrated CGRA design framework☆91Updated 7 months ago
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs☆167Updated last year
- CGRA framework with vectorization support.☆35Updated this week
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆51Updated 2 years ago
- CGRA Compilation Framework☆88Updated 2 years ago
- The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…☆38Updated 3 months ago
- ☆50Updated 3 months ago
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators.☆175Updated 2 months ago
- A hardware synthesis framework with multi-level paradigm☆41Updated 9 months ago
- An open source high level synthesis (HLS) tool built on top of LLVM☆125Updated last year
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆64Updated last year
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆43Updated last month
- A DSL for Systolic Arrays☆82Updated 6 years ago
- Public release☆56Updated 6 years ago
- Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)☆62Updated 3 years ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆115Updated last year
- The Task Parallel System Composer (TaPaSCo)☆110Updated 5 months ago
- An Open-Source Tool for CGRA Accelerators☆74Updated last month