lana555 / dynamatic
☆86Updated 11 months ago
Alternatives and similar repositories for dynamatic:
Users that are interested in dynamatic are comparing it to the libraries listed below
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆118Updated last week
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆59Updated 2 months ago
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆140Updated last year
- Benchmarks for Accelerator Design and Customized Architectures☆117Updated 4 years ago
- ☆39Updated this week
- An integrated CGRA design framework☆85Updated 3 months ago
- CGRA framework with vectorization support.☆24Updated this week
- Project repo for the POSH on-chip network generator☆43Updated last year
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆123Updated 2 years ago
- An Open-Source Tool for CGRA Accelerators☆58Updated last month
- ☆52Updated this week
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆38Updated 5 years ago
- Next generation CGRA generator☆108Updated this week
- The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…☆33Updated 3 weeks ago
- ☆57Updated last year
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆57Updated 4 months ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆119Updated 2 years ago
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆48Updated last year
- RapidStream TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.☆164Updated this week
- CGRA Compilation Framework☆82Updated last year
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆48Updated 7 years ago
- An Open-Source Tool for CGRA Accelerators☆18Updated 9 months ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆66Updated 5 years ago
- A hardware synthesis framework with multi-level paradigm☆36Updated last month
- A GPU acceleration flow for RTL simulation with batch stimulus☆102Updated 10 months ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 3 years ago
- A Style Guide for the Chisel Hardware Construction Language☆107Updated 3 years ago
- Public release☆49Updated 5 years ago
- DASS HLS Compiler☆28Updated last year