☆87Mar 5, 2024Updated 2 years ago
Alternatives and similar repositories for dynamatic
Users that are interested in dynamatic are comparing it to the libraries listed below
Sorting:
- DASS HLS Compiler☆29Oct 4, 2023Updated 2 years ago
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆54Jul 17, 2023Updated 2 years ago
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Aug 18, 2017Updated 8 years ago
- PandA-bambu public repository☆314Feb 10, 2026Updated 3 weeks ago
- DHLS (Dynamic High-Level Synthesis) compiler based on MLIR☆169Updated this week
- A formally verified high-level synthesis tool based on CompCert and written in Coq.☆98Jan 29, 2026Updated last month
- ☆60Aug 4, 2023Updated 2 years ago
- An LLVM pass to prove that an II works for the given loop for Vitis HLS☆11Aug 22, 2021Updated 4 years ago
- An open source high level synthesis (HLS) tool built on top of LLVM☆127Jun 11, 2024Updated last year
- ☆24Nov 10, 2020Updated 5 years ago
- Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)☆62Mar 17, 2022Updated 3 years ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆65Oct 9, 2024Updated last year
- Bridging polyhedral analysis tools to the MLIR framework☆119Sep 9, 2023Updated 2 years ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆127Jan 3, 2023Updated 3 years ago
- A scalable High-Level Synthesis framework on MLIR☆289May 15, 2024Updated last year
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators. UCLA-maintained.☆182Aug 16, 2025Updated 6 months ago
- The Shang high-level synthesis framework☆120May 29, 2014Updated 11 years ago
- ☆12Jul 20, 2022Updated 3 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Feb 17, 2021Updated 5 years ago
- Vitis HLS LLVM source code and examples☆403Sep 30, 2025Updated 5 months ago
- HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing (FPGA'19 Best Paper)☆341Apr 20, 2024Updated last year
- Stencil with Optimized Dataflow Architecture☆18Feb 27, 2024Updated 2 years ago
- Polyhedral High-Level Synthesis in MLIR☆35Mar 17, 2023Updated 2 years ago
- HeteroCL-MLIR dialect for accelerator design☆42Sep 18, 2024Updated last year
- HeteroGen: transpiling C to heterogeneous HLS code with automated test generation and program repair (ASPLOS 2022)☆17Sep 25, 2024Updated last year
- ☆16Oct 25, 2022Updated 3 years ago
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs (FPGA'18)☆169Nov 7, 2023Updated 2 years ago
- Build Customized FPGA Implementations for Vivado☆355Updated this week
- A Comprehensive Model-Based Analysis Framework for High Level Synthesis of Real Applications☆38Oct 20, 2020Updated 5 years ago
- A hardware synthesis framework with multi-level paradigm☆44Jan 10, 2025Updated last year
- Time-sensitive affine types for predictable hardware generation☆148Jan 5, 2026Updated 2 months ago
- An MLIR-based compiler from C/C++ to AMD-Xilinx Versal AIE☆17Aug 5, 2022Updated 3 years ago
- Allo Accelerator Design and Programming Framework (PLDI'24)☆352Feb 8, 2026Updated 3 weeks ago
- All Logi specific HDL code (platform specific interface, extension boards, specific hdl, etc)☆31Jan 25, 2016Updated 10 years ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆128Dec 20, 2022Updated 3 years ago
- Benchmarks for Accelerator Design and Customized Architectures☆136Apr 1, 2020Updated 5 years ago
- P4 compatible HLS modules☆11Apr 23, 2018Updated 7 years ago
- ☆126Updated this week
- ICCAD'23 Best Paper Award candidate: Robust GNN-based Representation Learning for HLS☆24May 23, 2024Updated last year