Alternatives and similar repositories for dynamatic:

Users that are interested in dynamatic are comparing it to the libraries listed below

• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆52Updated 5 years ago
• breagen / MachSuite
  Benchmarks for Accelerator Design and Customized Architectures
  ☆119Updated 4 years ago
• pnnl / OpenCGRA
  OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.
  ☆142Updated 2 years ago
• pnnl / soda-opt
  ☆41Updated this week
• tancheng / VectorCGRA
  CGRA framework with vectorization support.
  ☆27Updated this week
• tancheng / CGRA-Flow
  CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.
  ☆121Updated this week
• tancheng / CGRA-Mapper
  An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.
  ☆63Updated last week
• jianyicheng / DSS
  DASS HLS Compiler
  ☆29Updated last year
• UCLA-VAST / AutoBridge
  [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.
  ☆122Updated 2 years ago
• cwfletcher / buffets
  Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.
  ☆68Updated 5 years ago
• Xilinx / merlin-compiler
  ☆57Updated last year
• ecolab-nus / morpher
  An Open-Source Tool for CGRA Accelerators
  ☆58Updated 2 months ago
• pku-liang / Hector
  A hardware synthesis framework with multi-level paradigm
  ☆38Updated 2 months ago
• esl-epfl / OpenEdgeCGRA
  An Open-Hardware CGRA for accelerated computation on the edge.
  ☆20Updated 6 months ago
• cornell-brg / pymtl3-net
  Project repo for the POSH on-chip network generator
  ☆44Updated last year
• StanfordAHA / aha
  ☆54Updated this week
• pku-dasys / pillars
  An integrated CGRA design framework
  ☆86Updated 4 months ago
• StanfordAHA / garnet
  Next generation CGRA generator
  ☆110Updated this week
• circt-hls / circt-hls
  CIRCT-based HLS compilation flows, debugging, and cosimulation tools.
  ☆48Updated last year
• andrewboutros / rad-flow
  The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…
  ☆33Updated last month
• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆70Updated 5 years ago
• hngenc / systolic-array
  A DSL for Systolic Arrays
  ☆79Updated 6 years ago
• tancheng / mlir-cgra
  An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.
  ☆58Updated 5 months ago
• UCLA-VAST / RapidStream
  [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.
  ☆120Updated 2 years ago
• CMU-SAFARI / VAMPIRE
  An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …
  ☆38Updated 6 years ago
• UIUC-ChenLab / ScaleHLS-HIDA
  ☆46Updated 3 weeks ago
• Licheng-Guo / vivado-hls-broadcast-optimization
  [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency
  ☆32Updated 4 years ago
• rapidstream-org / rapidstream-tapa
  RapidStream TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.
  ☆165Updated this week
• Liu-Cheng / cycle-accurate-SystemC-simulator-over-ramulator
  An example of using Ramulator as memory model in a cycle-accurate SystemC Design
  ☆48Updated 7 years ago
• MPSLab-ASU / ccf
  CGRA Compilation Framework
  ☆83Updated last year