calyxir / calyx
Intermediate Language (IL) for Hardware Accelerator Generators
☆519Updated this week
Alternatives and similar repositories for calyx:
Users that are interested in calyx are comparing it to the libraries listed below
- Low Level Hardware Description — A foundation for building hardware design tools.☆409Updated 2 years ago
- A hardware compiler based on LLHD and CIRCT☆256Updated last year
- Time-sensitive affine types for predictable hardware generation☆143Updated 8 months ago
- Fearless hardware design☆176Updated last week
- Sail RISC-V model☆512Updated this week
- Sail architecture definition language☆691Updated this week
- Konata is an instruction pipeline visualizer for Onikiri2-Kanata/Gem5-O3PipeView formats. You can download the pre-built binaries from ht…☆432Updated 11 months ago
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆158Updated 2 months ago
- Tile based architecture designed for computing efficiency, scalability and generality☆249Updated 3 weeks ago
- ☆258Updated this week
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆220Updated last year
- Veryl: A Modern Hardware Description Language☆595Updated this week
- Working draft of the proposed RISC-V Bitmanipulation extension☆209Updated last year
- magma circuits☆259Updated 5 months ago
- ☆310Updated 6 months ago
- RISC-V support for LLVM projects (LLVM, Clang, ...)☆264Updated 8 months ago
- A Linux-capable RISC-V multicore for and by the world☆669Updated 3 weeks ago
- Bluespec Compiler (BSC)☆989Updated 3 weeks ago
- Working Draft of the RISC-V J Extension Specification☆182Updated last month
- RISC-V RV64GC emulator designed for RTL co-simulation☆223Updated 4 months ago
- FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility☆915Updated this week
- Vector Acceleration IP core for RISC-V*☆172Updated this week
- A dependency management tool for hardware projects.☆286Updated last month
- an educational compiler intermediate representation☆645Updated 2 weeks ago
- A 256-RISC-V-core system with low-latency access into shared L1 memory.☆288Updated this week
- high-performance RTL simulator☆154Updated 9 months ago
- Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework☆407Updated 2 weeks ago
- The batteries-included testing and formal verification library for Chisel-based RTL designs.☆231Updated 7 months ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆461Updated last month
- RISC-V Packed SIMD Extension☆144Updated last year