Alternatives and similar repositories for calyx

Users that are interested in calyx are comparing it to the libraries listed below

• fabianschuiki / llhd
  Low Level Hardware Description — A foundation for building hardware design tools.
  ☆423Updated 3 years ago
• cucapra / filament
  Fearless hardware design
  ☆183Updated 3 months ago
• fabianschuiki / moore
  A hardware compiler based on LLHD and CIRCT
  ☆264Updated 4 months ago
• cucapra / dahlia
  Time-sensitive affine types for predictable hardware generation
  ☆146Updated 2 weeks ago
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆274Updated last month
• riscv / sail-riscv
  Sail RISC-V model
  ☆627Updated last week
• tenstorrent / riscv-ocelot
  Ocelot: The Berkeley Out-of-Order Machine With V-EXT support
  ☆196Updated 2 weeks ago
• B-Lang-org / bsc
  Bluespec Compiler (BSC)
  ☆1,059Updated this week
• rems-project / sail
  Sail architecture definition language
  ☆806Updated this week
• pulp-platform / snitch
  ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!
  ☆226Updated 2 years ago
• mit-plv / koika
  A core language for rule-based hardware design 🦑
  ☆164Updated last month
• riscv / riscv-bitmanip
  Working draft of the proposed RISC-V Bitmanipulation extension
  ☆215Updated last year
• chipsalliance / t1
  ☆301Updated this week
• pulp-platform / bender
  A dependency management tool for hardware projects.
  ☆335Updated this week
• microsoft / kanagawa
  High level synthesis language for hardware design
  ☆68Updated this week
• riscv / riscv-j-extension
  Working Draft of the RISC-V J Extension Specification
  ☆191Updated last month
• phanrahan / magma
  magma circuits
  ☆263Updated last year
• EPFL-LAP / dynamatic
  DHLS (Dynamic High-Level Synthesis) compiler based on MLIR
  ☆146Updated this week
• veryl-lang / veryl
  Veryl: A Modern Hardware Description Language
  ☆828Updated this week
• shioyadan / Konata
  Konata is an instruction pipeline visualizer for Onikiri2-Kanata/Gem5-O3PipeView formats. You can download the pre-built binaries from ht…
  ☆499Updated last year
• pulp-platform / mempool
  A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.
  ☆312Updated this week
• pymtl / pymtl3
  Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
  ☆436Updated 2 months ago
• masc-ucsc / livehd
  Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
  ☆229Updated last week
• lowRISC / riscv-llvm
  RISC-V support for LLVM projects (LLVM, Clang, ...)
  ☆271Updated last year
• Xilinx / HLS
  Vitis HLS LLVM source code and examples
  ☆399Updated last month
• ucb-bar / berkeley-hardfloat
  ☆355Updated 2 months ago
• riscv / riscv-p-spec
  RISC-V Packed SIMD Extension
  ☆151Updated 2 weeks ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆235Updated last year
• ucsc-vama / essent
  high-performance RTL simulator
  ☆182Updated last year
• IntelLabs / riscv-vector
  Vector Acceleration IP core for RISC-V*
  ☆188Updated 6 months ago