Alternatives and similar repositories for calyx

Users that are interested in calyx are comparing it to the libraries listed below

• fabianschuiki / llhd
  Low Level Hardware Description — A foundation for building hardware design tools.
  ☆422Updated 3 years ago
• cucapra / filament
  Fearless hardware design
  ☆183Updated 2 months ago
• fabianschuiki / moore
  A hardware compiler based on LLHD and CIRCT
  ☆263Updated 4 months ago
• cucapra / dahlia
  Time-sensitive affine types for predictable hardware generation
  ☆145Updated 2 weeks ago
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆272Updated last month
• tenstorrent / riscv-ocelot
  Ocelot: The Berkeley Out-of-Order Machine With V-EXT support
  ☆189Updated last week
• riscv / sail-riscv
  Sail RISC-V model
  ☆622Updated this week
• rems-project / sail
  Sail architecture definition language
  ☆795Updated this week
• veryl-lang / veryl
  Veryl: A Modern Hardware Description Language
  ☆813Updated this week
• B-Lang-org / bsc
  Bluespec Compiler (BSC)
  ☆1,055Updated this week
• mit-plv / koika
  A core language for rule-based hardware design 🦑
  ☆163Updated 2 weeks ago
• riscv / riscv-j-extension
  Working Draft of the RISC-V J Extension Specification
  ☆191Updated 2 weeks ago
• shioyadan / Konata
  Konata is an instruction pipeline visualizer for Onikiri2-Kanata/Gem5-O3PipeView formats. You can download the pre-built binaries from ht…
  ☆487Updated last year
• chipsalliance / t1
  ☆295Updated this week
• pulp-platform / bender
  A dependency management tool for hardware projects.
  ☆332Updated this week
• pulp-platform / snitch
  ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!
  ☆226Updated last year
• Xilinx / HLS
  Vitis HLS LLVM source code and examples
  ☆397Updated last month
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆234Updated 11 months ago
• MoonbaseOtago / vroom
  VRoom! RISC-V CPU
  ☆511Updated last year
• EPFL-LAP / dynamatic
  DHLS (Dynamic High-Level Synthesis) compiler based on MLIR
  ☆141Updated this week
• masc-ucsc / livehd
  Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
  ☆226Updated this week
• lowRISC / riscv-llvm
  RISC-V support for LLVM projects (LLVM, Clang, ...)
  ☆270Updated last year
• llvm / circt
  Circuit IR Compilers and Tools
  ☆1,940Updated this week
• pymtl / pymtl3
  Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
  ☆432Updated 2 months ago
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆742Updated 3 weeks ago
• phanrahan / magma
  magma circuits
  ☆262Updated last year
• stanford-ppl / spatial
  Spatial: "Specify Parameterized Accelerators Through Inordinately Abstract Language"
  ☆285Updated last year
• firesim / firesim
  FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility
  ☆967Updated 4 months ago
• rsnikhil / Learn_Bluespec_and_RISCV_Design
  Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)
  ☆86Updated 2 weeks ago
• riscv / riscv-bitmanip
  Working draft of the proposed RISC-V Bitmanipulation extension
  ☆214Updated last year