Alternatives and similar repositories for api-generator-sifive:

Users that are interested in api-generator-sifive are comparing it to the libraries listed below

• freechipsproject / www.chisel-lang.org
  The home of the Chisel3 website
  ☆20Updated 8 months ago
• chick / visualizer
  Provides dot visualizations of chisel/firrtl circuites
  ☆12Updated 5 years ago
• verilator / uvm
  Universal Verification Methodology (UVM) base libraries, with edits for Verilator
  ☆26Updated 4 years ago
• pulp-platform / axi_llc
  ☆23Updated last month
• freechipsproject / chisel-coverage
  A coverage library for Chisel designs
  ☆11Updated 4 years ago
• kammoh / chisel-arithmetics
  Implementation of low-level hardware arithmatic operations in Chisel
  ☆8Updated 5 years ago
• SLink-Protocol / S-Link
  An Open Source Link Protocol and Controller
  ☆24Updated 3 years ago
• SpinalHDL / CocotbLib
  ☆15Updated last year
• TUM-LIS / lisnoc
  LIS Network-on-Chip Implementation
  ☆29Updated 8 years ago
• nvdla / tlm2c
  Backup: Library implementing a C TLM-2 style to bridge C models to SystemC TLM-2.0 (C++) from GreenSocs (https://git.greensocs.com/tlm/tl…
  ☆17Updated 6 years ago
• verilator / verilator_ext_tests
  Extended and external tests for Verilator testing
  ☆16Updated this week
• pulp-platform / axi_node
  AXI X-Bar
  ☆19Updated 4 years ago
• ucb-bar / OpenSoCFabric
  OpenSoC Fabric - A Network-On-Chip Generator
  ☆17Updated 7 years ago
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆24Updated 2 years ago
• dpretet / svlogger
  SystemVerilog Logger
  ☆17Updated 2 years ago
• MikeCovrado / GettingVerilatorStartedWithUVM
  Simple UVM environment for experimenting with Verilator.
  ☆17Updated last month
• riscv-verification / riscvISACOV
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆25Updated 4 months ago
• sifive / block-pio-sifive
  An example of on-boarding a PIO block in with duh and wake
  ☆12Updated 4 years ago
• RISCV-on-Microsemi-FPGA / CPUs
  CPUs
  ☆13Updated 4 years ago
• rggen / rggen-sv-rtl
  Common SystemVerilog RTL modules for RgGen
  ☆12Updated last week
• freechipsproject / chisel-cheatsheet
  Chisel Cheatsheet
  ☆32Updated last year
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆36Updated 9 months ago
• accellera-official / crave
  Constrained RAndom Verification Enviroment (CRAVE)
  ☆17Updated last year
• SymbioticEDA / getting-started-FV
  ☆18Updated 4 years ago
• waviousllc / wav-lpddr-sw
  Wavious DDR (WDDR) Physical interface (PHY) Software
  ☆19Updated 3 years ago
• vlotnik / uvm_modem
  UVM components for DSP tasks (MODulation/DEModulation)
  ☆14Updated 2 years ago
• hplp / aes_chisel
  Implementation of the Advanced Encryption Standard in Chisel
  ☆20Updated 2 years ago
• chipsalliance / OmnixtendEndpoint
  Hardware implementation of an OmniXtend Memory Endpoint/Lowest Point of Coherence.
  ☆16Updated 9 months ago
• amichai-bd / riscv-multi-core-lotr
  RISCV core RV32I/E.4 threads in a ring architecture
  ☆31Updated last year
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆59Updated 3 months ago