cucapra / filament
Fearless hardware design
☆175Updated last week
Alternatives and similar repositories for filament:
Users that are interested in filament are comparing it to the libraries listed below
- Intermediate Language (IL) for Hardware Accelerator Generators☆527Updated this week
- A hardware compiler based on LLHD and CIRCT☆256Updated last year
- Low Level Hardware Description — A foundation for building hardware design tools.☆411Updated 3 years ago
- A core language for rule-based hardware design 🦑☆151Updated 6 months ago
- Time-sensitive affine types for predictable hardware generation☆143Updated 9 months ago
- Verilator Porcelain☆47Updated last year
- End-to-end synthesis and P&R toolchain☆82Updated last month
- Veryl: A Modern Hardware Description Language☆622Updated this week
- An HDL embedded in Rust.☆198Updated last year
- Working Draft of the RISC-V J Extension Specification☆184Updated 2 months ago
- The highest performace Cray-like RISC-V Vector in the world.☆265Updated this week
- wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.☆60Updated 2 weeks ago
- A Hardware Description Language based on the Rust Programming Language☆204Updated this week
- A configurable and approachable tool for FPGA debugging and rapid prototyping.☆135Updated last month
- A new Hardware Design Language that keeps you in the driver's seat☆79Updated last week
- Tile based architecture designed for computing efficiency, scalability and generality☆252Updated this week
- Minimax: a Compressed-First, Microcoded RISC-V CPU☆210Updated last year
- A dependency management tool for hardware projects.☆295Updated this week
- A computer for human beings.☆44Updated 6 months ago
- 🦀 No nonsense hardware testing/simulation in Rust 🛠️ | Verilog, Spade, Veryl☆42Updated last month
- RISC-V Formal Verification Framework☆137Updated this week
- Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)☆72Updated 7 months ago
- A collection of common Bluespec interfaces/modules.☆98Updated last year
- Where Lions Roam: RISC-V on the VELDT☆259Updated 9 months ago
- magma circuits☆260Updated 6 months ago
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆162Updated 3 months ago
- A configurable RTL to bitstream FPGA toolchain☆28Updated last month
- An rv32i inspired ISA, SIMT GPU implementation in system-verilog.☆184Updated 2 months ago
- The SiFive wake build tool☆90Updated this week
- FOSS Flow For FPGA☆386Updated 4 months ago