cucapra / filamentLinks
Fearless hardware design
☆181Updated last month
Alternatives and similar repositories for filament
Users that are interested in filament are comparing it to the libraries listed below
Sorting:
- Intermediate Language (IL) for Hardware Accelerator Generators☆548Updated this week
- A hardware compiler based on LLHD and CIRCT☆262Updated 3 months ago
- Low Level Hardware Description — A foundation for building hardware design tools.☆421Updated 3 years ago
- A core language for rule-based hardware design 🦑☆161Updated 3 months ago
- A new Hardware Design Language that keeps you in the driver's seat☆116Updated this week
- Time-sensitive affine types for predictable hardware generation☆145Updated 3 weeks ago
- Verilator Porcelain☆49Updated last year
- Working Draft of the RISC-V J Extension Specification☆191Updated last month
- 🦀 No-nonsense hardware testing/simulation in Rust 🛠️ | Verilog, Spade, Veryl☆65Updated last month
- End-to-end synthesis and P&R toolchain☆89Updated 2 weeks ago
- wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.☆89Updated last month
- A Hardware Description Language that doesn't make you want to pull your hair out | read-only mirror of https://gitlab.com/spade-lang/spad…☆31Updated last week
- ☆290Updated this week
- Minimax: a Compressed-First, Microcoded RISC-V CPU☆223Updated last year
- A collection of common Bluespec interfaces/modules.☆102Updated last year
- An HDL embedded in Rust.☆200Updated last year
- Veryl: A Modern Hardware Description Language☆801Updated this week
- A computer for human beings.☆45Updated 10 months ago
- RISCV Core written in Calyx☆17Updated last year
- The SiFive wake build tool☆91Updated 2 weeks ago
- The LLHD reference simulator.☆39Updated 5 years ago
- Logic circuit analysis and optimization☆42Updated last month
- A dependency management tool for hardware projects.☆323Updated 3 weeks ago
- Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)☆83Updated 2 months ago
- ☆40Updated 4 years ago
- An rv32i inspired ISA, SIMT GPU implementation in system-verilog.☆206Updated 7 months ago
- This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory prot…☆81Updated this week
- Where Lions Roam: RISC-V on the VELDT☆260Updated last month
- Sail RISC-V model☆613Updated last week
- A configurable RTL to bitstream FPGA toolchain☆44Updated 2 weeks ago