Alternatives and similar repositories for embeddedHaskellAetherling

Users that are interested in embeddedHaskellAetherling are comparing it to the libraries listed below

• David-Durst / aetherling
  Create auto-scheduled data-parallel pipelines in hardware with user-friendly Python
  ☆13Updated 4 years ago
• cucapra / latte21
  Languages, Tools, and Techniques for Accelerator Design
  ☆33Updated 4 years ago
• vegaluisjose / reticle
  ☆40Updated 4 years ago
• cucapra / dahlia
  Time-sensitive affine types for predictable hardware generation
  ☆147Updated last month
• ymherklotz / vericert
  A formally verified high-level synthesis tool based on CompCert and written in Coq.
  ☆96Updated 3 months ago
• gussmith23 / lakeroad
  FPGA synthesis tool powered by program synthesis
  ☆52Updated 2 months ago
• jameshegarty / rigel
  Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FP…
  ☆56Updated 5 years ago
• rdaly525 / coreir
  ☆104Updated 3 years ago
• apl-cornell / PDL
  A Hardware Pipeline Description Language
  ☆49Updated 5 months ago
• vegaluisjose / vast
  Verilog AST
  ☆21Updated 2 years ago
• dillonhuff / clockwork
  A polyhedral compiler for hardware accelerators
  ☆59Updated last year
• agurfinkel / btor2mlir
  BTOR2 MLIR project
  ☆26Updated last year
• gussmith23 / glenside
  A pure, low-level tensor program representation enabling tensor program optimization via program rewriting. See the web demo at https://g…
  ☆71Updated 6 months ago
• SiliconSemantics / firrtlator
  firrtlator is a FIRRTL C++ library
  ☆23Updated 8 years ago
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆74Updated 5 years ago
• etherzhhb / Shang
  The Shang high-level synthesis framework
  ☆120Updated 11 years ago
• TeamVoss / VossII
  The source code to the Voss II Hardware Verification Suite
  ☆56Updated last week
• cdonovick / peak
  Peak : Processor Specification Language ala Newell and Bell's ISP
  ☆20Updated 2 years ago
• UCSBarchlab / Charm
  A Language for Closed-form High-level ARchitecture Modeling
  ☆21Updated 5 years ago
• mit-plv / koika
  A core language for rule-based hardware design 🦑
  ☆166Updated this week
• cliffordwolf / bextdep
  Reference Hardware Implementations of Bit Extract/Deposit Instructions
  ☆25Updated 8 years ago
• johnwickerson / memalloy
  Memory consistency modelling using Alloy
  ☆31Updated 4 years ago
• uwplse / rake
  compiling DSLs to high-level hardware instructions
  ☆23Updated 3 years ago
• StanfordAHA / Halide-to-Hardware_archive
  ☆82Updated 10 months ago
• mikeurbach / egg-netlist-synthesizer
  Using e-graphs to synthesize netlists from boolean logic.
  ☆14Updated 2 years ago
• whaaswijk / percy
  An advanced header-only exact synthesis library
  ☆29Updated 3 years ago
• sfu-arch / muir
  ☆24Updated 5 years ago
• zhemao / chisel-float
  Floating point modules for CHISEL
  ☆32Updated 11 years ago
• cornell-zhang / datuner
  DATuner Repository
  ☆17Updated 7 years ago
• POETSII / tinsel
  Manythread RISC-V overlay for FPGA clusters
  ☆38Updated 2 months ago