Alternatives and similar repositories for embeddedHaskellAetherling

Users that are interested in embeddedHaskellAetherling are comparing it to the libraries listed below

• David-Durst / aetherling
  Create auto-scheduled data-parallel pipelines in hardware with user-friendly Python
  ☆13Updated 4 years ago
• vegaluisjose / reticle
  ☆40Updated 3 years ago
• cucapra / latte21
  Languages, Tools, and Techniques for Accelerator Design
  ☆33Updated 3 years ago
• TeamVoss / VossII
  The source code to the Voss II Hardware Verification Suite
  ☆56Updated 2 months ago
• Ekdohibs / PolyGen
  PolyGen is a code generator for the polyhedral model, written and proved in Coq.
  ☆10Updated 4 years ago
• gussmith23 / lakeroad
  FPGA synthesis tool powered by program synthesis
  ☆49Updated last month
• agurfinkel / btor2mlir
  BTOR2 MLIR project
  ☆26Updated last year
• cucapra / dahlia
  Time-sensitive affine types for predictable hardware generation
  ☆143Updated 11 months ago
• ymherklotz / vericert
  A formally verified high-level synthesis tool based on CompCert and written in Coq.
  ☆92Updated last year
• apl-cornell / PDL
  A Hardware Pipeline Description Language
  ☆45Updated last year
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆73Updated 4 years ago
• vegaluisjose / vast
  Verilog AST
  ☆21Updated last year
• dillonhuff / clockwork
  A polyhedral compiler for hardware accelerators
  ☆59Updated 11 months ago
• gussmith23 / glenside
  A pure, low-level tensor program representation enabling tensor program optimization via program rewriting. See the web demo at https://g…
  ☆70Updated 3 weeks ago
• mikeurbach / egg-netlist-synthesizer
  Using e-graphs to synthesize netlists from boolean logic.
  ☆14Updated last year
• rdaly525 / coreir
  ☆103Updated 2 years ago
• mit-plv / koika
  A core language for rule-based hardware design 🦑
  ☆156Updated 2 weeks ago
• UCSBarchlab / Charm
  A Language for Closed-form High-level ARchitecture Modeling
  ☆21Updated 5 years ago
• CakeML / hardware
  Verilog development and verification project for HOL4
  ☆26Updated 2 months ago
• johnwickerson / memalloy
  Memory consistency modelling using Alloy
  ☆29Updated 4 years ago
• daniellustig / riscv-memory-model
  A formalization of the RVWMO (RISC-V) memory model
  ☆33Updated 3 years ago
• sfu-arch / muir
  ☆24Updated 4 years ago
• whaaswijk / percy
  An advanced header-only exact synthesis library
  ☆26Updated 2 years ago
• mc-imperial / multicore-test-harness
  A multicore microprocessor test harness for measuring interference
  ☆14Updated 5 years ago
• diffblue / hw-cbmc
  The HW-CBMC and EBMC Model Checkers for Verilog
  ☆79Updated this week
• etherzhhb / Shang
  The Shang high-level synthesis framework
  ☆120Updated 11 years ago
• aqjune / mlir-tv
  A translation validation framework for MLIR
  ☆87Updated 3 months ago
• zhemao / chisel-float
  Floating point modules for CHISEL
  ☆32Updated 10 years ago
• PrincetonUniversity / ILAng
  A Modeling and Verification Platform for SoCs using ILAs
  ☆78Updated 11 months ago
• uwsampl / lastlayer
  Towards Hardware and Software Continuous Integration
  ☆13Updated 5 years ago