☆30Oct 16, 2022Updated 3 years ago
Alternatives and similar repositories for embeddedHaskellAetherling
Users that are interested in embeddedHaskellAetherling are comparing it to the libraries listed below
Sorting:
- Create auto-scheduled data-parallel pipelines in hardware with user-friendly Python☆13Mar 29, 2021Updated 4 years ago
- Optimal approximate sampling from discrete probability distributions☆18Mar 9, 2021Updated 4 years ago
- Provides Spatial with front-end support from popular machine learning frameworks☆34Sep 30, 2019Updated 6 years ago
- A polyhedral compiler for hardware accelerators☆59Jul 24, 2024Updated last year
- Time-sensitive affine types for predictable hardware generation☆148Jan 5, 2026Updated last month
- CoreIR Symbolic Analyzer☆74Oct 27, 2020Updated 5 years ago
- Part of paper: Massively Parallel Combinational Binary Neural Networks for Edge Processing☆12Jun 27, 2019Updated 6 years ago
- Absinthe is an optimization framework to fuse and tile stencil codes in one shot☆14Jul 17, 2019Updated 6 years ago
- Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation☆233Updated this week
- A C++ Library for Hardware Design and Simulation☆15May 17, 2020Updated 5 years ago
- Floating point modules for CHISEL☆32Nov 2, 2014Updated 11 years ago
- ☆104Jun 27, 2022Updated 3 years ago
- ☆37Jun 1, 2022Updated 3 years ago
- A core language for rule-based hardware design 🦑☆172Dec 10, 2025Updated 2 months ago
- ☆173Apr 20, 2021Updated 4 years ago
- An integrated context-aware scanner and parser generator☆22Dec 4, 2023Updated 2 years ago
- Implementation of Lightweight Modular Staging (LMS) in Python☆48Apr 2, 2019Updated 6 years ago
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators. UCLA-maintained.☆182Aug 16, 2025Updated 6 months ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆127Jan 3, 2023Updated 3 years ago
- A high-level performance analysis tool for FPGA-based accelerators☆19Jun 2, 2017Updated 8 years ago
- Peak : Processor Specification Language ala Newell and Bell's ISP☆20Dec 5, 2023Updated 2 years ago
- A Simple Abstract Interpreter, built for teaching purposes☆20May 13, 2020Updated 5 years ago
- ☆82Feb 7, 2025Updated last year
- Szalinski: A Tool for Synthesizing Structured CAD Models with Equality Saturation and Inverse Transformations☆55Sep 1, 2025Updated 6 months ago
- HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing (FPGA'19 Best Paper)☆341Apr 20, 2024Updated last year
- DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language☆93Feb 17, 2026Updated last week
- ☆57Feb 19, 2017Updated 9 years ago
- Darkroom Core☆48Oct 7, 2017Updated 8 years ago
- ☆87Mar 5, 2024Updated last year
- DMon Prototype for OSDI 2021 Artifact Evaluation☆24May 4, 2021Updated 4 years ago
- Gallina to Bedrock2 compilation toolkit☆65Updated this week
- Language-independent, search-based program repair -- just your cup of tea! ☕☆30Jul 9, 2024Updated last year
- soap - Structural Optimisation of Arithmetic Programs☆24May 9, 2016Updated 9 years ago
- ☆30Mar 2, 2021Updated 4 years ago
- Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FP…☆57Sep 15, 2020Updated 5 years ago
- Open source fpga project leveraging vtr CAD flow.☆26Mar 4, 2023Updated 2 years ago
- ☆24Nov 10, 2020Updated 5 years ago
- ☆26Sep 3, 2020Updated 5 years ago
- Debuggable hardware generator☆71Feb 17, 2023Updated 3 years ago