☆30Oct 16, 2022Updated 3 years ago
Alternatives and similar repositories for embeddedHaskellAetherling
Users that are interested in embeddedHaskellAetherling are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Create auto-scheduled data-parallel pipelines in hardware with user-friendly Python☆13Mar 29, 2021Updated 5 years ago
- Scala staging framework☆18Jul 13, 2018Updated 8 years ago
- A polyhedral compiler for hardware accelerators☆59Jul 24, 2024Updated 2 years ago
- Time-sensitive affine types for predictable hardware generation☆153Jan 5, 2026Updated 7 months ago
- Fork of Hipacc generating code for Vivado HLS and Altera OpenCL☆24Oct 8, 2018Updated 7 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- CoreIR Symbolic Analyzer☆75Oct 27, 2020Updated 5 years ago
- Provides Spatial with front-end support from popular machine learning frameworks☆34Sep 30, 2019Updated 6 years ago
- Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation☆239Updated this week
- Optimal approximate sampling from discrete probability distributions☆18Mar 9, 2021Updated 5 years ago
- Absinthe is an optimization framework to fuse and tile stencil codes in one shot☆14Jul 17, 2019Updated 7 years ago
- Part of paper: Massively Parallel Combinational Binary Neural Networks for Edge Processing☆12Jun 27, 2019Updated 7 years ago
- DFiant HDL (DFHDL): A Mutli-abstraction Hardware Descripition Language and Framework☆97Updated this week
- ☆106Jun 27, 2022Updated 4 years ago
- Try the active community-maintained version with binary releases at https://github.com/tuna/tapa . This is the UCLA publication version.☆193Mar 8, 2026Updated 5 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A core language for rule-based hardware design 🦑☆181Dec 10, 2025Updated 8 months ago
- Open source RTL simulation acceleration on commodity hardware☆35Apr 13, 2023Updated 3 years ago
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆39Jan 16, 2025Updated last year
- ☆37Jun 1, 2022Updated 4 years ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆127Jan 3, 2023Updated 3 years ago
- Generate and tune custom architectures for sparse linear algebra☆15Jan 20, 2018Updated 8 years ago
- ☆24Nov 10, 2020Updated 5 years ago
- A domain-specific language and compiler for image processing☆78Mar 20, 2021Updated 5 years ago
- ☆86Mar 5, 2024Updated 2 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing (FPGA'19 Best Paper)☆338Apr 20, 2024Updated 2 years ago
- Peak : Processor Specification Language ala Newell and Bell's ISP☆21Dec 5, 2023Updated 2 years ago
- An advanced automated reasoning tool for memory consistency model specifications.☆25Dec 6, 2021Updated 4 years ago
- A hardware compiler based on LLHD and CIRCT☆271Jun 30, 2025Updated last year
- Cross EDA Abstraction and Automation☆42Updated this week
- Block diagrams in ASCII☆18Oct 17, 2025Updated 9 months ago
- ☆11Sep 14, 2020Updated 5 years ago
- Implementation of Lightweight Modular Staging (LMS) in Python☆48Apr 2, 2019Updated 7 years ago
- A Vivado HLS Command Line Helper Tool☆36Oct 6, 2021Updated 4 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- The implementation of the Elevate language☆32Mar 21, 2025Updated last year
- ☆172Apr 20, 2021Updated 5 years ago
- A C++ Library for Hardware Design and Simulation☆15May 17, 2020Updated 6 years ago
- Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FP…☆57Sep 15, 2020Updated 5 years ago
- Extra minimal TypeScript implementation of Hindley-Milner type inference☆38Aug 1, 2026Updated last week
- A high-level performance analysis tool for FPGA-based accelerators☆19Jun 2, 2017Updated 9 years ago
- Low Level Hardware Description — A foundation for building hardware design tools.☆436Apr 20, 2022Updated 4 years ago