kaist-cp / shakeflowLinks
ShakeFlow: Functional Hardware Description with Latency-Insensitive Interface Combinators (ASPLOS 2023)
☆56Updated 10 months ago
Alternatives and similar repositories for shakeflow
Users that are interested in shakeflow are comparing it to the libraries listed below
Sorting:
- HazardFlow: Modular Hardware Design of Pipelined Circuits with Hazards IMPORTANT: DON'T FORK!☆20Updated last year
- ☆44Updated last year
- ☆133Updated 2 years ago
- Memento: A Framework for Detectable Recoverability in Persistent Memory (PLDI 2023)☆18Updated 2 years ago
- KAIST Educational Virtualization☆15Updated last year
- KECC: KAIST Educational C Compiler. IMPORTANT: DON'T FORK!☆174Updated 6 months ago
- A translation validation framework for MLIR☆89Updated 8 months ago
- ☆23Updated 4 years ago
- CIRC: Concurrent Immediate Reference Counting☆53Updated last year
- A Hardware Pipeline Description Language☆49Updated 5 months ago
- ☆19Updated 2 years ago
- ☆16Updated last week
- Support for language highlighting of KECC(KAIST Educational C Compiler) IR☆12Updated 3 years ago
- ☆22Updated 4 years ago
- ☆40Updated 4 years ago
- compiling DSLs to high-level hardware instructions☆23Updated 3 years ago
- A core language for rule-based hardware design 🦑☆166Updated last week
- Time-sensitive affine types for predictable hardware generation☆147Updated last month
- A set of tools that automate the execution of scarab simulations☆18Updated last week
- 컴퓨터 신기술 특강☆10Updated 2 years ago
- The Coq development of A Promising Semantics for Relaxed-Memory Concurrency☆42Updated last year
- CHERI-RISC-V model written in Sail☆66Updated 5 months ago
- A Coq framework to support structural design and proof of hardware cache-coherence protocols☆14Updated 3 years ago
- Virtuoso is a fast, accurate and versatile simulation framework designed for virtual memory research. Virtuoso uses a new simulation met…☆78Updated 2 months ago
- A pure, low-level tensor program representation enabling tensor program optimization via program rewriting. See the web demo at https://g…☆72Updated 6 months ago
- High level synthesis language for hardware design☆78Updated this week
- A enumerator for MLIR, relying on the information given by IRDL.☆20Updated 2 weeks ago
- The Educational RISC-V Toolset in Python☆38Updated 2 years ago
- ☆63Updated 3 months ago
- HeteroRefactor: Refactoring for Heterogeneous Computing with FPGA☆10Updated 4 months ago