Alternatives and similar repositories for evoapproxlib:

Users that are interested in evoapproxlib are comparing it to the libraries listed below

• karthisugumar / CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2
  A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…
  ☆147Updated 5 years ago
• arasi15 / CNN-Accelerator-Implementation-based-on-Eyerissv2
  ☆103Updated 4 years ago
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆93Updated 4 years ago
• vaughnbetz / COFFE
  ☆41Updated 6 months ago
• georgia-tech-synergy-lab / SIGMA
  RTL implementation of Flex-DPE.
  ☆98Updated 5 years ago
• BoooC / CNN-Accelerator-Based-on-Eyeriss-v2
  A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network
  ☆54Updated last month
• pku-dasys / pillars
  An integrated CGRA design framework
  ☆87Updated this week
• BUAA-CI-LAB / Literatures-on-SRAM-based-CIM
  A reading list for SRAM-based Compute-In-Memory (CIM) research.
  ☆53Updated last month
• maomran / softmax
  Verilog implementation of Softmax function
  ☆59Updated 2 years ago
• xliu0709 / WinoCNN
  An HLS based winograd systolic CNN accelerator
  ☆50Updated 3 years ago
• arc-research-lab / CHARM
  CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture
  ☆131Updated this week
• cornell-zhang / FracBNN
  FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations
  ☆91Updated 3 years ago
• taoyilee / clacc
  Deep Learning Accelerator (Convolution Neural Networks)
  ☆177Updated 7 years ago
• rapidstream-org / rapidstream-tapa
  RapidStream TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.
  ☆165Updated this week
• Xilinx / ResNet50-PYNQ
  Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ
  ☆57Updated 3 years ago
• ac-optimus / Convolution-using-systolic-arrays
  ☆63Updated 6 years ago
• amiq-consulting / CNN-using-HLS
  Convolutional Neural Network Using High Level Synthesis
  ☆86Updated 4 years ago
• ecolab-nus / morpher
  An Open-Source Tool for CGRA Accelerators
  ☆59Updated 2 months ago
• skycrapers / AM-Lib
  ☆22Updated last year
• neasotho / SystolicArray_FPGA
  Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board
  ☆13Updated 4 years ago
• suoglu / Fixed-Floating-Point-Adder-Multiplier
  16-bit Adder Multiplier hardware on Digilent Basys 3
  ☆70Updated last year
• KULeuven-MICAS / zigzag
  HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators
  ☆141Updated 3 weeks ago
• KULeuven-MICAS / stream
  Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.
  ☆48Updated last month
• djtfoo / lenet5-verilog
  A Verilog design of LeNet-5, a Convolutional Neural Network architecture
  ☆27Updated 4 years ago
• leo47007 / TPU-Tensor-Processing-Unit
  IC implementation of TPU
  ☆112Updated 5 years ago
• Linger0 / SRAM-Compute-In-Memory
  A collection of research papers on SRAM-based compute-in-memory architectures.
  ☆28Updated last year
• UCLA-VAST / FlexCNN
  ☆71Updated 2 years ago
• lirui-shanghaitech / CNN-Accelerator-VLSI
  Convolutional accelerator kernel, target ASIC & FPGA
  ☆185Updated last year
• WenqiJiang / VGG16_FPGA_Accelerator
  A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…
  ☆30Updated 5 years ago
• Dazhuzhu-github / systolic-array
  verilog实现TPU中的脉动阵列计算卷积的module
  ☆90Updated 3 years ago