A Convolutional Neural Network Accelerator implementation on FPGA, xilinx （xczu7ev-ffvc1156-2-i）, The inference of yolov8 took 60ms.
☆515Jul 17, 2025Updated 7 months ago
Alternatives and similar repositories for Neural-Network-Accelerator
Users that are interested in Neural-Network-Accelerator are comparing it to the libraries listed below
Sorting:
- IC implementation of Systolic Array for TPU☆340Oct 21, 2024Updated last year
- 网络训练、图像预处理以及部分hend功能是基于pc端实现的，只有主干网络部署在fpga上，片上资源无法支持整个网络所需资源，建议添加外部存储及DDR☆143Jul 20, 2023Updated 2 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆136Jul 22, 2025Updated 7 months ago
- [ICTA'21] First Prize Winner of the 2021 DIGILENT Cup, China College Integrated Circuit Competition☆270Apr 1, 2024Updated last year
- FPGA-based SNN Accelerator Toy☆33Dec 17, 2025Updated 2 months ago
- 2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器，支持yolov3-tiny的第一层卷积层计算，可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆224Oct 16, 2025Updated 4 months ago
- verilog实现systolic array及配套IO☆12Dec 2, 2024Updated last year
- Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.☆23May 7, 2024Updated last year
- Convolutional accelerator kernel, target ASIC & FPGA☆245Apr 10, 2023Updated 2 years ago
- A network slimming-based pruning method for YOLOv8.☆39Jun 10, 2024Updated last year
- This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.☆33Aug 13, 2024Updated last year
- Verilog AXI components for FPGA implementation☆1,970Feb 27, 2025Updated last year
- 在FPGA上面实现一个NPU计算单元。能够执行矩阵运算（ADD/ADDi/ADDs/MULT/MULTi/DOT等）、图像处理运算（CONV/POOL等）、非线性映射（RELU/TANH/SIGM等）。☆293Aug 16, 2018Updated 7 years ago
- You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size o…☆231Mar 24, 2024Updated last year
- 帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目☆5,273May 15, 2022Updated 3 years ago
- 包含了SOC设计中的通用IP，如外设、总线结构、基础、验证等☆135Feb 25, 2026Updated last week
- The Ultra-Low Power RISC-V Core☆1,748Aug 6, 2025Updated 7 months ago
- A demo for accelerating YOLOv2 in xilinx's fpga pynq/zedboard☆896Jul 29, 2024Updated last year
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆85Nov 26, 2025Updated 3 months ago
- An efficient spatial accelerator enabling hybrid sparse attention mechanisms for long sequences☆31Mar 7, 2024Updated last year
- Vivado诸多IP，包括图像处理等☆234Jul 28, 2024Updated last year
- Implement Tiny YOLO v3 on ZYNQ☆312Apr 14, 2025Updated 10 months ago
- Eyeriss‑V1 CNN Hardware Accelerator (Verilog) fully parametric. This repository contains the complete Verilog implementation of a functio…☆26Apr 7, 2025Updated 10 months ago
- OpenExSys_NoC a mesh-based network on chip IP.☆20Dec 1, 2023Updated 2 years ago
- IC implementation of TPU☆148Dec 18, 2019Updated 6 years ago
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆129Jan 20, 2025Updated last year
- ☆33Sep 17, 2021Updated 4 years ago
- a Real-time image recognition project with RTL accelerator and ZYNQ Architecture☆66Apr 8, 2024Updated last year
- ☆14Jun 22, 2022Updated 3 years ago
- [DATE'2025, TCAD'2025] Terafly : A Multi-Node FPGA Based Accelerator Design for Efficient Cooperative Inference in LLMs☆28Nov 13, 2025Updated 3 months ago
- 简单的未优化的SRT除法器☆12Jun 16, 2024Updated last year
- ☆241Apr 8, 2024Updated last year
- Efficient FPGA-Based Accelerator for Convolutional Neural Networks☆49Jul 31, 2024Updated last year
- 一个开源的FPGA神经网络加速器。☆189Sep 4, 2023Updated 2 years ago
- PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications☆43May 5, 2023Updated 2 years ago
- Edge-MoE: Memory-Efficient Multi-Task Vision Transformer Architecture with Task-level Sparsity via Mixture-of-Experts☆134May 10, 2024Updated last year
- 基于verilog实现了ISP图像处理IP☆316Nov 28, 2022Updated 3 years ago
- The official NaplesPU hardware code repository☆22Jul 27, 2019Updated 6 years ago
- AXI4 with a FIFO integrated with VIP☆22Feb 29, 2024Updated 2 years ago