bonanyan / attentionlegoLinks
Attentionlego
☆12Updated last year
Alternatives and similar repositories for attentionlego
Users that are interested in attentionlego are comparing it to the libraries listed below
Sorting:
- Accelerate multihead attention transformer model using HLS for FPGA☆11Updated last year
- ☆16Updated last year
- Open-source of MSD framework☆16Updated last year
- ☆31Updated 4 years ago
- Collection of kernel accelerators optimised for LLM execution☆18Updated 2 months ago
- A collection of research papers on SRAM-based compute-in-memory architectures.☆28Updated last year
- [ASPLOS 2024] CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators☆38Updated last year
- MICRO22 artifact evaluation for Sparseloop☆44Updated 2 years ago
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆32Updated this week
- ☆27Updated 2 months ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆54Updated 3 months ago
- C++ code for HLS FPGA implementation of transformer☆17Updated 9 months ago
- A co-design architecture on sparse attention☆52Updated 3 years ago
- ☆44Updated 2 years ago
- [TVLSI'23] This repository contains the source code for the paper "FireFly: A High-Throughput Hardware Accelerator for Spiking Neural Net…☆19Updated last year
- Model LLM inference on single-core dataflow accelerators☆10Updated 4 months ago
- ☆18Updated 2 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆54Updated this week
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆39Updated 2 years ago
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆46Updated last year
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆79Updated 3 years ago
- ☆12Updated last year
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆20Updated 2 years ago
- [FPGA 2024]FPGA Accelerator for Imbalanced SpMV using HLS☆13Updated 4 months ago
- ☆41Updated 11 months ago
- A bit-level sparsity-awared multiply-accumulate process element.☆16Updated 11 months ago
- An efficient spatial accelerator enabling hybrid sparse attention mechanisms for long sequences☆28Updated last year
- This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.☆19Updated 10 months ago
- ☆17Updated last month
- Open source RTL implementation of Tensor Core, Sparse Tensor Core, BitWave and SparSynergy in the article: "SparSynergy: Unlocking Flexib…☆18Updated 2 months ago