chrisneuf / Deep-Neural-Network-Hardware-Accelerator
My implementation of an FPGA Deep Neural Network Hardware Accelerator, moved from my bitbucket
☆25Updated 5 years ago
Alternatives and similar repositories for Deep-Neural-Network-Hardware-Accelerator:
Users that are interested in Deep-Neural-Network-Hardware-Accelerator are comparing it to the libraries listed below
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆27Updated last year
- This is a verilog implementation of 4x4 systolic array multiplier☆43Updated 4 years ago
- Hardware accelerator for convolutional neural networks☆34Updated 2 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆40Updated 5 months ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆14Updated 3 years ago
- tpu-systolic-array-weight-stationary☆20Updated 3 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆136Updated 5 years ago
- ☆99Updated 4 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆45Updated 4 years ago
- ☆21Updated 4 years ago
- ☆60Updated 6 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆73Updated 3 years ago
- A collection of tutorials for the fpgaConvNet framework.☆38Updated 4 months ago
- FPGA based Vision Transformer accelerator (Harvard CS205)☆97Updated last year
- Verilog implementation of Softmax function☆54Updated 2 years ago
- AMD University Program HLS tutorial☆75Updated 3 months ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆26Updated 5 years ago
- High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.☆33Updated 6 months ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆27Updated 4 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆22Updated 2 years ago
- eyeriss-chisel3☆40Updated 2 years ago
- This repository contains full code of Softmax Layer in Verilog☆16Updated 4 years ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆54Updated 3 years ago
- A verilog implementation for Network-on-Chip☆71Updated 6 years ago
- IC implementation of TPU☆95Updated 5 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆85Updated 4 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆175Updated last year
- Verilog Implementation of 32-bit Floating Point Adder☆35Updated 4 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆65Updated last year
- ☆27Updated 5 years ago