chrisneuf / Deep-Neural-Network-Hardware-Accelerator
My implementation of an FPGA Deep Neural Network Hardware Accelerator, moved from my bitbucket
☆22Updated 5 years ago
Related projects ⓘ
Alternatives and complementary repositories for Deep-Neural-Network-Hardware-Accelerator
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆20Updated last year
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆32Updated 2 months ago
- ☆93Updated 4 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆129Updated 4 years ago
- Hardware accelerator for convolutional neural networks☆26Updated 2 years ago
- ☆60Updated 5 years ago
- tpu-systolic-array-weight-stationary☆18Updated 3 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆12Updated 3 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆68Updated 2 years ago
- This is a verilog implementation of 4x4 systolic array multiplier☆39Updated 4 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆45Updated 4 years ago
- Verilog implementation of Softmax function☆48Updated 2 years ago
- A systolic array matrix multiplier☆23Updated 5 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆21Updated 2 years ago
- ☆26Updated 5 years ago
- IC implementation of Systolic Array for TPU☆153Updated last month
- A DNN Accelerator implemented with RTL.☆61Updated last year
- A verilog implementation for Network-on-Chip☆67Updated 6 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆83Updated 4 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆63Updated last year
- An HLS based winograd systolic CNN accelerator☆48Updated 3 years ago
- A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs.☆16Updated 7 months ago
- A collection of tutorials for the fpgaConvNet framework.☆32Updated 2 months ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆10Updated 3 years ago
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆29Updated 5 years ago
- High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.☆29Updated 3 months ago
- ☆11Updated 5 years ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆127Updated 5 months ago
- Convolutional accelerator kernel, target ASIC & FPGA☆168Updated last year
- Single Long Short Term Memory (LSTM) cell : Verilog Implementation☆29Updated 4 years ago