My implementation of an FPGA Deep Neural Network Hardware Accelerator, moved from my bitbucket
☆28Jul 31, 2019Updated 6 years ago
Alternatives and similar repositories for Deep-Neural-Network-Hardware-Accelerator
Users that are interested in Deep-Neural-Network-Hardware-Accelerator are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SystemVerilog files for lab project on a DNN hardware accelerator☆18Jun 22, 2021Updated 4 years ago
- Hardware accelerator for convolutional neural networks☆68Aug 9, 2022Updated 3 years ago
- ☆13Aug 21, 2019Updated 6 years ago
- PLL Simulator in SystemC-AMS☆11Jun 2, 2023Updated 2 years ago
- Verilog RTL Implementation of DNN☆10Jun 26, 2018Updated 7 years ago
- Wordpress hosting with auto-scaling - Free Trial • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆45Sep 26, 2023Updated 2 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆11Jan 27, 2022Updated 4 years ago
- Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.☆13May 14, 2019Updated 6 years ago
- Accelerator for Hyperdimensional Computing (HDC)☆35May 5, 2024Updated last year
- ☆15Mar 9, 2026Updated last month
- Extending BookSim2.0 and HotSpot6.0 for Power, Performance and Thermal evaluation of 3D NoC Architectures☆13Aug 9, 2019Updated 6 years ago
- Accelerating a Classic 3D Video Game (The DOOM) on Heterogeneous Reconfigurable MPSoCs☆20Jun 4, 2020Updated 5 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆182Dec 14, 2019Updated 6 years ago
- NVDLA small config implementation on Zynq ZCU104 (evaluation)☆24Mar 25, 2019Updated 7 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Official implementation of "Searching for Winograd-aware Quantized Networks" (MLSys'20)☆26Oct 3, 2023Updated 2 years ago
- SOC system using verilog on FPGA devices.☆10Jan 11, 2016Updated 10 years ago
- Deep learning accelerator for convolutional layer (convolution operation) and fully-connected layer(matrix-multiplication).☆20Nov 18, 2018Updated 7 years ago
- Google Apps Script to aggregate Google Scholar Alerts into a digest email☆14Nov 29, 2024Updated last year
- High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.☆42Jul 25, 2024Updated last year
- Convolutional accelerator kernel, target ASIC & FPGA☆252Apr 10, 2023Updated 3 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆138Jul 22, 2025Updated 8 months ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Apr 10, 2020Updated 6 years ago
- Superscalar Out-of-Order NPU Design on FPGA☆13May 17, 2024Updated last year
- Deploy open-source AI quickly and easily - Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK So…☆112Apr 3, 2020Updated 6 years ago
- Systolic Three Matrix Multiplier for Graph Convolutional Networks using High Level Synthesis☆23Jul 29, 2022Updated 3 years ago
- Various low power labs using sky130☆13Sep 3, 2021Updated 4 years ago
- ☆21Apr 8, 2025Updated last year
- This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times …☆28Jul 4, 2019Updated 6 years ago
- The code for AIM2022 compressed image super-resolution☆11Nov 30, 2022Updated 3 years ago
- codes of the paper Rate Gradient Approximation Attack Threats Deep Spiking Neural Networks (CVPR 2023)☆16Aug 19, 2024Updated last year
- Modified the conventional JPEG compression algorithm with Lloyd-Max Quantizer. Implemented in MATLAB and tested on Xilinx Artix-7 FPGA.☆18Aug 31, 2020Updated 5 years ago
- [IPSN 2024] Lifelong Intelligence Beyond the Edge using Hyperdimensional Computing☆13May 16, 2024Updated last year
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- This repository is an excuse to learn about Convolutional Neural Networks by implementing one in FPGA. The main goal is to learn, and to …☆12Jul 12, 2020Updated 5 years ago
- This is a circular buffer controller used in FPGA.☆35Jan 12, 2016Updated 10 years ago
- Computer-Aided VLSI System Design☆24Oct 24, 2024Updated last year
- Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017☆31Sep 22, 2018Updated 7 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Jan 19, 2021Updated 5 years ago
- This project uses OpenCV for object tracking to control player position in Unity3d tennis game. Uses Colour tracking and UDP socket to tr…☆26Sep 16, 2025Updated 6 months ago
- AI Accelerators-SC23-tutorial Repository☆12Nov 12, 2023Updated 2 years ago