My implementation of an FPGA Deep Neural Network Hardware Accelerator, moved from my bitbucket
☆30Jul 31, 2019Updated 7 years ago
Alternatives and similar repositories for Deep-Neural-Network-Hardware-Accelerator
Users that are interested in Deep-Neural-Network-Hardware-Accelerator are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SystemVerilog files for lab project on a DNN hardware accelerator☆18Jun 22, 2021Updated 5 years ago
- Hardware accelerator for convolutional neural networks☆76Aug 9, 2022Updated 4 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆47Sep 26, 2023Updated 2 years ago
- PLL Simulator in SystemC-AMS☆11Jun 2, 2023Updated 3 years ago
- Verilog RTL Implementation of DNN☆10Jun 26, 2018Updated 8 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- SOC system using verilog on FPGA devices.☆10Jan 11, 2016Updated 10 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆11Jan 27, 2022Updated 4 years ago
- ☆15Apr 12, 2026Updated 4 months ago
- Accelerator for Hyperdimensional Computing (HDC)☆36May 5, 2024Updated 2 years ago
- NVDLA small config implementation on Zynq ZCU104 (evaluation)☆24Mar 25, 2019Updated 7 years ago
- Verilog implementation of a pre-trained handwritten digit recognition simple neural network.☆35Dec 26, 2023Updated 2 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆185Dec 14, 2019Updated 6 years ago
- Extending BookSim2.0 and HotSpot6.0 for Power, Performance and Thermal evaluation of 3D NoC Architectures☆14Aug 9, 2019Updated 7 years ago
- Official implementation of "Searching for Winograd-aware Quantized Networks" (MLSys'20)☆27Oct 3, 2023Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.☆46Jul 25, 2024Updated 2 years ago
- This repository contains MATLAB code which can be used to generate simulink model and HDL code for implementation on FPGA. Since HDL code…☆14May 6, 2020Updated 6 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆258Apr 10, 2023Updated 3 years ago
- SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK So…☆114Apr 3, 2020Updated 6 years ago
- Deep learning accelerator for convolutional layer (convolution operation) and fully-connected layer(matrix-multiplication).☆20Nov 18, 2018Updated 7 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Apr 10, 2020Updated 6 years ago
- Superscalar Out-of-Order NPU Design on FPGA☆16May 17, 2024Updated 2 years ago
- Repository of files associated with the webinar on analog layout using magic and klayout with Matt Venn.☆17Apr 13, 2023Updated 3 years ago
- Tensor Processing Unit implementation in Verilog☆16Updated this week
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Vstream - Video Analytics pipeline with Hardware based accelerations (dev - stage)☆10Feb 2, 2024Updated 2 years ago
- Systolic Three Matrix Multiplier for Graph Convolutional Networks using High Level Synthesis☆24Jul 29, 2022Updated 4 years ago
- Modified the conventional JPEG compression algorithm with Lloyd-Max Quantizer. Implemented in MATLAB and tested on Xilinx Artix-7 FPGA.☆18Aug 31, 2020Updated 5 years ago
- ☆22Apr 8, 2025Updated last year
- The code for AIM2022 compressed image super-resolution☆11Nov 30, 2022Updated 3 years ago
- Computer-Aided VLSI System Design☆25Oct 24, 2024Updated last year
- codes of the paper Rate Gradient Approximation Attack Threats Deep Spiking Neural Networks (CVPR 2023)☆16Aug 19, 2024Updated last year
- ☆16May 6, 2026Updated 3 months ago
- [IPSN 2024] Lifelong Intelligence Beyond the Edge using Hyperdimensional Computing☆14May 16, 2024Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- This repository is an excuse to learn about Convolutional Neural Networks by implementing one in FPGA. The main goal is to learn, and to …☆12Jul 12, 2020Updated 6 years ago
- This is a circular buffer controller used in FPGA.☆36Jan 12, 2016Updated 10 years ago
- Face recognition with loss of softmax, sphereface, cosface, arcface in pytorch of python3☆10Apr 27, 2020Updated 6 years ago
- Not All Patches Are Equal: Hierarchical Dataset Condensation for Single Image Super-Resolution☆10May 7, 2024Updated 2 years ago
- Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017☆31Sep 22, 2018Updated 7 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Jan 19, 2021Updated 5 years ago
- Google Apps Script to aggregate Google Scholar Alerts into a digest email☆15Nov 29, 2024Updated last year