Youssefmdany / Design-and-UVM-TB-of-RISC-V-Microprocessor
Design and UVM-TB of RISC -V Microprocessor
☆12Updated 2 months ago
Related projects: ⓘ
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆11Updated 7 months ago
- verification of simple axi-based cache☆16Updated 5 years ago
- CORE-V MCU UVM Environment and Test Bench☆16Updated 2 months ago
- ☆14Updated last year
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆9Updated last year
- ☆23Updated 4 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆39Updated 3 years ago
- ☆31Updated 2 years ago
- To design test bench of the APB protocol☆16Updated 3 years ago
- ☆18Updated 9 years ago
- Andes Vector Extension support added to riscv-dv☆14Updated 4 years ago
- General Purpose AXI Direct Memory Access☆44Updated 4 months ago
- Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀☆13Updated 6 months ago
- Implementation of the PCIe physical layer☆28Updated 4 years ago
- ☆19Updated this week
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆25Updated this week
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆17Updated last year
- Xilinx AXI VIP example of use☆29Updated 3 years ago
- ☆16Updated 5 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆27Updated 5 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆29Updated last year
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆24Updated last year
- UVM resource from github, run simulation use YASAsim flow☆24Updated 4 years ago
- AXI Interconnect☆44Updated 3 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆28Updated 3 years ago
- Direct Access Memory for MPSoC☆12Updated this week
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆15Updated 10 years ago
- SoC Based on ARM Cortex-M3☆24Updated 4 months ago
- ☆20Updated 3 years ago
- SystemVerilog examples and projects☆17Updated 5 years ago