Alternatives and similar repositories for cnnhwpe

Users that are interested in cnnhwpe are comparing it to the libraries listed below

• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆40Updated 3 years ago
• ac-optimus / Convolution-using-systolic-arrays
  ☆72Updated 7 years ago
• SingularityKChen / dl_accelerator
  Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions
  ☆206Updated 5 years ago
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆62Updated last month
• matutani / nocgen
  NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers
  ☆76Updated 6 years ago
• kuladeepsaireddy / OpenNoc
  ☆40Updated 6 years ago
• IA-C-Lab-Fudan / Chisel-FFT-generator
  FFT generator using Chisel
  ☆63Updated 4 years ago
• suoglu / Fixed-Floating-Point-Adder-Multiplier
  16-bit Adder Multiplier hardware on Digilent Basys 3
  ☆83Updated 2 years ago
• pulp-platform / fpu
  ☆58Updated 6 years ago
• cnrv / CNRV-FPU
  Basic floating-point components for RISC-V processors
  ☆67Updated 6 years ago
• romulus0914 / CNN_VGG19_verilog
  Convolution Neural Network of vgg19 model in verilog
  ☆49Updated 8 years ago
• LCAI-TIHU / HW
  LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…
  ☆44Updated 3 years ago
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆39Updated 4 years ago
• hyoukjun / OpenSMART
  Public release
  ☆58Updated 6 years ago
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆67Updated 2 years ago
• anan-cn / Open-Source-Network-on-Chip-Router-RTL
  ☆82Updated 11 years ago
• bakhshalipour / NoC-Verilog
  A verilog implementation for Network-on-Chip
  ☆81Updated 8 years ago
• bsc-loca / sauria
  SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…
  ☆79Updated 2 months ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆208Updated 5 months ago
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆114Updated 5 years ago
• soDLA-publishment / soDLA
  Chisel implementation of the NVIDIA Deep Learning Accelerator (NVDLA), with self-driving accelerated
  ☆236Updated last month
• cea-wind / SimpleTPU
  A FPGA Based CNN accelerator, following Google's TPU V1.
  ☆169Updated 6 years ago
• yportne13 / SpinalResNet
  AdderNet ResNet20 for cifar10 written in SpinalHDL
  ☆35Updated 4 years ago
• THU-DSP-LAB / ventus-gpgpu-verilog
  GPGPU supporting RISCV-V, developed with verilog HDL
  ☆138Updated 11 months ago
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆197Updated 3 years ago
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆136Updated 5 years ago
• wzc810049078 / systolic-array-matrix-multiplier
  A systolic array matrix multiplier
  ☆30Updated 6 years ago
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆84Updated 7 years ago
• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆75Updated 5 years ago
• leo47007 / TPU-Tensor-Processing-Unit
  IC implementation of TPU
  ☆147Updated 6 years ago