chenhaoc / cnnhwpeLinks
☆66Updated 3 years ago
Alternatives and similar repositories for cnnhwpe
Users that are interested in cnnhwpe are comparing it to the libraries listed below
Sorting:
- ☆71Updated 6 years ago
- eyeriss-chisel3☆40Updated 3 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆82Updated 2 years ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆204Updated 5 years ago
- ☆57Updated 6 years ago
- ☆38Updated 6 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆71Updated 5 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated this week
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆108Updated 5 years ago
- Convolution Neural Network of vgg19 model in verilog☆49Updated 7 years ago
- FFT generator using Chisel☆62Updated 4 years ago
- A verilog implementation for Network-on-Chip☆77Updated 7 years ago
- An open-source UCIe controller implementation☆76Updated 2 weeks ago
- ☆66Updated 3 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆42Updated 2 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆68Updated last week
- AdderNet ResNet20 for cifar10 written in SpinalHDL☆35Updated 4 years ago
- Public release☆58Updated 6 years ago
- ☆79Updated 11 years ago
- GPGPU supporting RISCV-V, developed with verilog HDL☆126Updated 9 months ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆32Updated 4 years ago
- HLS for Networks-on-Chip☆37Updated 4 years ago
- Verilog implementation of Softmax function☆77Updated 3 years ago
- An AXI4 crossbar implementation in SystemVerilog☆183Updated 3 months ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆162Updated 6 years ago
- IC implementation of TPU☆140Updated 5 years ago
- Chisel implementation of the NVIDIA Deep Learning Accelerator (NVDLA), with self-driving accelerated☆234Updated 10 months ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Updated 6 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆67Updated last year
- Network on Chip Implementation written in SytemVerilog☆194Updated 3 years ago