chenhaoc / cnnhwpe
☆65Updated 2 years ago
Alternatives and similar repositories for cnnhwpe:
Users that are interested in cnnhwpe are comparing it to the libraries listed below
- eyeriss-chisel3☆40Updated 2 years ago
- Basic floating-point components for RISC-V processors☆65Updated 5 years ago
- ☆63Updated 6 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆71Updated last year
- FFT generator using Chisel☆58Updated 3 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆55Updated last month
- General Purpose AXI Direct Memory Access☆49Updated 11 months ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆98Updated 4 years ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆189Updated 4 years ago
- IC implementation of TPU☆121Updated 5 years ago
- ☆31Updated 5 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆61Updated last year
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆33Updated 5 years ago
- ☆50Updated 2 years ago
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆14Updated 4 years ago
- AdderNet ResNet20 for cifar10 written in SpinalHDL☆32Updated 4 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆62Updated 5 years ago
- Project where we conceptualized and designed a simple neural network accelerator, loosely based on the Eyeriss architecture, to accelerat…☆11Updated 5 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆74Updated 7 years ago
- ☆43Updated 6 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆30Updated 4 years ago
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆50Updated 7 years ago
- Hardware accelerator for convolutional neural networks☆43Updated 2 years ago
- A verilog implementation for Network-on-Chip☆73Updated 7 years ago
- ☆55Updated 4 years ago
- Convolution Neural Network of vgg19 model in verilog☆46Updated 7 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆178Updated 7 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆155Updated 5 years ago
- Public release☆51Updated 5 years ago
- Pure digital components of a UCIe controller☆61Updated 2 weeks ago