chenhaoc / cnnhwpeLinks
☆66Updated 3 years ago
Alternatives and similar repositories for cnnhwpe
Users that are interested in cnnhwpe are comparing it to the libraries listed below
Sorting:
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆198Updated 5 years ago
- eyeriss-chisel3☆41Updated 3 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated last week
- ☆65Updated 6 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆67Updated 5 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆104Updated 4 years ago
- ☆60Updated 2 years ago
- AdderNet ResNet20 for cifar10 written in SpinalHDL☆35Updated 4 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆77Updated 2 years ago
- IC implementation of TPU☆128Updated 5 years ago
- FFT generator using Chisel☆62Updated 3 years ago
- A verilog implementation for Network-on-Chip☆76Updated 7 years ago
- Public release☆57Updated 5 years ago
- Convolution Neural Network of vgg19 model in verilog☆49Updated 7 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆164Updated 5 years ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆158Updated 6 years ago
- ☆34Updated 6 years ago
- General Purpose AXI Direct Memory Access☆57Updated last year
- ☆53Updated 6 years ago
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆14Updated 5 years ago
- ☆77Updated 10 years ago
- Parameterized Booth Multiplier in Verilog 2001☆50Updated 2 years ago
- GPGPU supporting RISCV-V, developed with verilog HDL☆108Updated 6 months ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆41Updated 2 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆31Updated 4 years ago
- hardware design of universal NPU(CNN accelerator) for various convolution neural network☆139Updated 5 months ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Updated 5 years ago
- Verilog implementation of Softmax function☆67Updated 3 years ago
- An AXI4 crossbar implementation in SystemVerilog☆169Updated last week
- Vector processor for RISC-V vector ISA☆126Updated 4 years ago