chenhaoc / cnnhwpe
☆64Updated 2 years ago
Alternatives and similar repositories for cnnhwpe:
Users that are interested in cnnhwpe are comparing it to the libraries listed below
- Basic floating-point components for RISC-V processors☆64Updated 5 years ago
- eyeriss-chisel3☆40Updated 2 years ago
- FFT generator using Chisel☆57Updated 3 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆58Updated last year
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆50Updated 2 weeks ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆89Updated 4 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆67Updated last year
- General Purpose AXI Direct Memory Access☆48Updated 9 months ago
- ☆62Updated 6 years ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆180Updated 4 years ago
- Convolution Neural Network of vgg19 model in verilog☆46Updated 7 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆141Updated 5 years ago
- ☆36Updated 6 years ago
- ☆29Updated 5 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆73Updated 7 years ago
- IC implementation of TPU☆100Updated 5 years ago
- A verilog implementation for Network-on-Chip☆73Updated 7 years ago
- FPGA/AES/LeNet/VGG16☆95Updated 6 years ago
- ☆70Updated 10 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 3 years ago
- ☆41Updated 2 years ago
- This repository contains all the parameters you need to synthesize the AlexNet by using Vivado High Level Synthesis.☆21Updated 6 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆59Updated 5 years ago
- Tests for example Rocket Custom Coprocessors☆70Updated 5 years ago
- ☆53Updated 4 years ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆51Updated 4 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆27Updated 4 years ago
- Examples for creating AXI-interfaced peripherals in Chisel☆74Updated 9 years ago
- HLS for Networks-on-Chip☆33Updated 4 years ago
- ☆41Updated 6 years ago