chenhaoc / cnnhwpe
☆64Updated 2 years ago
Related projects ⓘ
Alternatives and complementary repositories for cnnhwpe
- Basic floating-point components for RISC-V processors☆64Updated 4 years ago
- eyeriss-chisel3☆39Updated 2 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆83Updated 4 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆56Updated 10 months ago
- FFT generator using Chisel☆56Updated 3 years ago
- ☆60Updated 5 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆63Updated last year
- IC implementation of TPU☆87Updated 4 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆48Updated 5 months ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆129Updated 4 years ago
- round robin arbiter☆68Updated 10 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆24Updated 3 years ago
- A verilog implementation for Network-on-Chip☆68Updated 6 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆69Updated 6 years ago
- Convolution Neural Network of vgg19 model in verilog☆44Updated 6 years ago
- An AXI4 crossbar implementation in SystemVerilog☆123Updated this week
- ☆62Updated 3 months ago
- A matrix extension proposal for AI applications under RISC-V architecture☆109Updated 3 weeks ago
- ☆26Updated 5 years ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆176Updated 4 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆12Updated 3 years ago
- ☆93Updated 4 years ago
- General Purpose AXI Direct Memory Access☆44Updated 6 months ago
- FPGA/AES/LeNet/VGG16☆88Updated 6 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆57Updated 4 years ago
- Top project for RISC-V Matrix extension proposal and related opensource implementations.☆23Updated 7 months ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆29Updated 5 years ago
- ☆67Updated 10 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆166Updated 6 years ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆121Updated 5 years ago