chenhaoc / cnnhwpeLinks
☆66Updated 3 years ago
Alternatives and similar repositories for cnnhwpe
Users that are interested in cnnhwpe are comparing it to the libraries listed below
Sorting:
- eyeriss-chisel3☆41Updated 3 years ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆201Updated 5 years ago
- ☆68Updated 6 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆81Updated 2 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆67Updated 5 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated last month
- FFT generator using Chisel☆62Updated 4 years ago
- A verilog implementation for Network-on-Chip☆77Updated 7 years ago
- Convolution Neural Network of vgg19 model in verilog☆49Updated 7 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆104Updated 5 years ago
- ☆36Updated 6 years ago
- Basic floating-point components for RISC-V processors☆66Updated 5 years ago
- AdderNet ResNet20 for cifar10 written in SpinalHDL☆35Updated 4 years ago
- GPGPU supporting RISCV-V, developed with verilog HDL☆113Updated 7 months ago
- Public release☆56Updated 6 years ago
- Pure digital components of a UCIe controller☆71Updated 3 weeks ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆42Updated 2 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆66Updated last year
- IC implementation of TPU☆132Updated 5 years ago
- ☆54Updated 6 years ago
- HLS for Networks-on-Chip☆36Updated 4 years ago
- Hardware accelerator for convolutional neural networks☆57Updated 3 years ago
- ☆78Updated 10 years ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆159Updated 6 years ago
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- An AXI4 crossbar implementation in SystemVerilog☆175Updated last month
- ☆64Updated 3 years ago
- hardware design of universal NPU(CNN accelerator) for various convolution neural network☆152Updated 7 months ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆58Updated last year
- Verilog implementation of Softmax function☆70Updated 3 years ago