General CNN_Accelerator design.卷积神经网络加速器设计。在PYNQ-Z2 FPGA开发板上实现了卷积池化全连接层等硬件加速计算。
☆91Mar 6, 2025Updated last year
Alternatives and similar repositories for General-CNN-Accelerator
Users that are interested in General-CNN-Accelerator are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 基于Xilinx FPGA的通用型 CNN卷积神经网络加速器,本设计基于KV260板卡,MpSoC架构均可移植☆19Dec 13, 2024Updated last year
- yolov5-acceleration-fpga☆11Jun 25, 2025Updated 9 months ago
- 我设计了一些数字集成电路的教学实验,供大家学习~☆36Jan 23, 2025Updated last year
- 【入门项目】基于PYNQ-Z2实现手写数字识别卷积神经网络硬件加速器☆185Apr 10, 2023Updated 2 years ago
- 一个开源的FPGA神经网络加速器。☆191Sep 4, 2023Updated 2 years ago
- Efficient FPGA-Based Accelerator for Convolutional Neural Networks☆54Jul 31, 2024Updated last year
- Attentionlego☆13Jan 24, 2024Updated 2 years ago
- ☆31Nov 7, 2024Updated last year
- Sparse CNN Accelerator targeting Intel FPGA☆12Aug 26, 2021Updated 4 years ago
- AI Chip project☆34Jul 14, 2021Updated 4 years ago
- 使用FPGA实现CNN模型☆15Jun 21, 2019Updated 6 years ago
- R2MDC FFT/IFFT processor adaptive to 64/128/256/512 point☆18Dec 23, 2025Updated 3 months ago
- ☆16Apr 6, 2022Updated 3 years ago
- 基于FPGA的二维卷积识别任务☆26Apr 29, 2023Updated 2 years ago
- 东秦第五届龙芯班仓库☆10Oct 22, 2023Updated 2 years ago
- 可运行☆39Jul 1, 2022Updated 3 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆136Jul 22, 2025Updated 8 months ago
- 基于FPGA的数字识别-实时视频处理的定点卷积神经网络实现☆368May 2, 2023Updated 2 years ago
- Implementation of CNN on ZYNQ FPGA to classify handwritten numbers using MNIST database☆579Feb 19, 2021Updated 5 years ago
- An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017☆24May 20, 2019Updated 6 years ago
- Hardware accelerator for convolutional neural networks☆67Aug 9, 2022Updated 3 years ago
- 中文:☆109Nov 29, 2019Updated 6 years ago
- Verilog program☆16Jul 27, 2020Updated 5 years ago
- OpenNNA2.0,一个基于C语言(C99)的开源神经网络推理框架☆94Aug 3, 2023Updated 2 years ago
- 本项目使用 Vivado 和 SDK 工程软件上完成系统设计和生成相关部署文件,并在 ARM+FPGA 完成项目部署,实现通过摄取图片并通过 ARM+FPGA 综合部署和加速识别算法,并通过显示驱动,在显示屏上显示摄像头原图和识别结果。☆10Aug 12, 2022Updated 3 years ago
- A CNN accelerator design inspired by MIT Eyeriss project☆20Aug 14, 2021Updated 4 years ago
- [ICTA'21] First Prize Winner of the 2021 DIGILENT Cup, China College Integrated Circuit Competition☆276Apr 1, 2024Updated last year
- simple experiments to reproduce the CReLU paper☆12Jun 17, 2016Updated 9 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆18Jun 22, 2021Updated 4 years ago
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆15Jun 23, 2020Updated 5 years ago
- Edge-MoE: Memory-Efficient Multi-Task Vision Transformer Architecture with Task-level Sparsity via Mixture-of-Experts☆134May 10, 2024Updated last year
- ☆11Apr 29, 2022Updated 3 years ago
- Dataflow compiler for QNN inference on FPGAs☆954Updated this week
- You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size o…☆234Mar 24, 2024Updated 2 years ago
- 2023集创赛国二。基于脉动 阵列写的一个简单的卷积层加速器,支持yolov3-tiny的第一层卷积层计算,可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆231Oct 16, 2025Updated 5 months ago
- This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented wi…☆20Sep 3, 2019Updated 6 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Oct 2, 2019Updated 6 years ago
- Template for project1 TPU☆23May 1, 2021Updated 4 years ago
- FPGA创新设计大赛全国二等奖,Multi-functional Game Console Based on RISC-V.(基于紫光FPGA的RSIC V多功能游戏机)☆11Aug 16, 2024Updated last year