General CNN_Accelerator design.卷积神经网络加速器设计。在PYNQ-Z2 FPGA开发板上实现了卷积池化全连接层等硬件加速计算。
☆97Apr 25, 2026Updated last week
Alternatives and similar repositories for General-CNN-Accelerator
Users that are interested in General-CNN-Accelerator are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 基于Xilinx FPGA的通用型 CNN卷积神经网络加速器,本设计基于KV260板卡,MpSoC架构均可移植☆20Dec 13, 2024Updated last year
- yolov5-acceleration-fpga☆11Jun 25, 2025Updated 10 months ago
- 我设计了一些数字集成电路的教学实验,供大家学习~☆38Jan 23, 2025Updated last year
- 【入门项目】基于PYNQ-Z2实现手写数字识别卷积神经网络硬件加速器☆192Apr 10, 2023Updated 3 years ago
- 一个开源的FPGA神经网络加速器。☆195Sep 4, 2023Updated 2 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Efficient FPGA-Based Accelerator for Convolutional Neural Networks☆56Jul 31, 2024Updated last year
- Attentionlego☆13Jan 24, 2024Updated 2 years ago
- ☆33Nov 7, 2024Updated last year
- AI Chip project☆34Jul 14, 2021Updated 4 years ago
- ES-203 Computer Organization & Architecture CNN on FPGA board☆18Feb 23, 2022Updated 4 years ago
- 使用FPGA实现CNN模型☆15Jun 21, 2019Updated 6 years ago
- R2MDC FFT/IFFT processor adaptive to 64/128/256/512 point☆18Dec 23, 2025Updated 4 months ago
- ☆17Apr 6, 2022Updated 4 years ago
- 东秦第五届龙芯班仓库☆11Oct 22, 2023Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆143Jul 22, 2025Updated 9 months ago
- 基于FPGA的数字识别-实时视频处理的定点卷积神经网络实现☆372May 2, 2023Updated 3 years ago
- Implementation of CNN on ZYNQ FPGA to classify handwritten numbers using MNIST database☆593Feb 19, 2021Updated 5 years ago
- ☆15May 28, 2024Updated last year
- Hardware accelerator for convolutional neural networks☆70Aug 9, 2022Updated 3 years ago
- 中文:☆109Nov 29, 2019Updated 6 years ago
- Verilog program☆16Jul 27, 2020Updated 5 years ago
- OpenNNA2.0,一个基于C语言(C99)的开源神经网络推理框架☆95Aug 3, 2023Updated 2 years ago
- 本项目使用 Vivado 和 SDK 工程软件上完成系统设计和生成相关部署文件,并在 ARM+FPGA 完成项目部署,实现通过摄取图片并通过 ARM+FPGA 综合部署和加速识别算法,并通过显示驱动,在显示屏上显示摄像头原图和识别结果。☆10Aug 12, 2022Updated 3 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- A CNN accelerator design inspired by MIT Eyeriss project☆20Aug 14, 2021Updated 4 years ago
- [ICTA'21] First Prize Winner of the 2021 DIGILENT Cup, China College Integrated Circuit Competition☆280Apr 1, 2024Updated 2 years ago
- simple experiments to reproduce the CReLU paper☆12Jun 17, 2016Updated 9 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆18Jun 22, 2021Updated 4 years ago
- Zynq/FPGA实现CNN手写数字(0-9)识别☆41Dec 14, 2024Updated last year
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆16Jun 23, 2020Updated 5 years ago
- Edge-MoE: Memory-Efficient Multi-Task Vision Transformer Architecture with Task-level Sparsity via Mixture-of-Experts☆138May 10, 2024Updated last year
- Professor: C.H. Yang☆10Aug 16, 2025Updated 8 months ago
- FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference☆175Jun 9, 2023Updated 2 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- ☆11Apr 29, 2022Updated 4 years ago
- You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size o…☆247Mar 24, 2024Updated 2 years ago
- Dataflow compiler for QNN inference on FPGAs☆977Updated this week
- This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented wi…☆21Sep 3, 2019Updated 6 years ago
- 2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器,支持yolov3-tiny的第一层卷积层计算,可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆243Oct 16, 2025Updated 6 months ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Oct 2, 2019Updated 6 years ago
- Template for project1 TPU☆23May 1, 2021Updated 5 years ago