Efficient FPGA-Based Accelerator for Convolutional Neural Networks
☆49Jul 31, 2024Updated last year
Alternatives and similar repositories for Efficient-FPGA-CNN-Accelerator
Users that are interested in Efficient-FPGA-CNN-Accelerator are comparing it to the libraries listed below
Sorting:
- 基于Xilinx FPGA的通用型 CNN卷积神经网络加速器，本设计基于KV260板卡，MpSoC架构均可移植☆18Dec 13, 2024Updated last year
- The goal of this design is to use the PYNQ-Z2 development board to design a general convolution neural network accelerator. And through r…☆11Sep 30, 2020Updated 5 years ago
- Hardware accelerator for convolutional neural networks☆65Aug 9, 2022Updated 3 years ago
- bitfusion verilog implementation☆12Feb 21, 2022Updated 4 years ago
- Eyeriss Hardware Accelerator for Machine Learning☆13May 29, 2022Updated 3 years ago
- ☆16Jan 18, 2025Updated last year
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆17Feb 27, 2021Updated 5 years ago
- ES-203 Computer Organization & Architecture CNN on FPGA board☆17Feb 23, 2022Updated 4 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆45Jun 24, 2022Updated 3 years ago
- FPGA Design of a Spiking Neural Network.☆46May 15, 2024Updated last year
- An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017☆23May 20, 2019Updated 6 years ago
- 基于FPGA的二维卷积识别任务☆26Apr 29, 2023Updated 2 years ago
- ☆11Dec 10, 2025Updated 2 months ago
- An automated HDC platform☆11Updated this week
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Apr 10, 2020Updated 5 years ago
- General CNN_Accelerator design.卷积神经网络加速器设计。在PYNQ-Z2 FPGA开发板上实现了卷积池化全连接层等硬件加速计算。☆89Mar 6, 2025Updated 11 months ago
- A C++ implementation of a 3 layer Gated Recurrent Unit (GRU) using no libraries other than Eigen for Matrices.☆22Jan 28, 2020Updated 6 years ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆21Feb 28, 2021Updated 5 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆136Jul 22, 2025Updated 7 months ago
- ☆30Jun 8, 2022Updated 3 years ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆182Jun 20, 2024Updated last year
- The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL☆37Sep 25, 2019Updated 6 years ago
- hardware design of universal NPU(CNN accelerator) for various convolution neural network☆166Mar 5, 2025Updated 11 months ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆43Sep 26, 2023Updated 2 years ago
- verilog CNN generator for FPGA☆34Jan 4, 2021Updated 5 years ago
- The official implementation of HPCA 2025 paper, Prosperity: Accelerating Spiking Neural Networks via Product Sparsity☆37Aug 9, 2025Updated 6 months ago
- HTB_Write_Ups☆27Feb 25, 2024Updated 2 years ago
- System Verilog code describing a fully combinational binarized neural network.☆34Jul 6, 2018Updated 7 years ago
- EE 272B - VLSI Design Project☆15Jun 24, 2021Updated 4 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Oct 2, 2019Updated 6 years ago
- ☆11Dec 17, 2023Updated 2 years ago
- Used for hardware trojan detection（Based on Trust_Hub）☆10Jul 30, 2019Updated 6 years ago
- ☆11Dec 10, 2025Updated 2 months ago
- Alpha64 R10000 Two-Way Superscalar Processor☆11May 6, 2019Updated 6 years ago
- Implementation of a Systolic Array based sorting engine on an FPGA using Verilog☆11May 11, 2017Updated 8 years ago
- ☆57Nov 29, 2025Updated 3 months ago
- Human activity recognition using hyperdimensional computing based on Kinect's skeleton data☆11Jun 5, 2017Updated 8 years ago
- Code for the ISCAS23 paper "The Hardware Impact of Quantization and Pruning for Weights in Spiking Neural Networks"☆11Apr 20, 2023Updated 2 years ago
- A Verilog implementation of a hand-written digit recognition Neural Network☆10Nov 16, 2024Updated last year