BoChen-Ye / Tiny_LeViT_Hardware_Accelerator
This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.
☆13Updated 8 months ago
Alternatives and similar repositories for Tiny_LeViT_Hardware_Accelerator:
Users that are interested in Tiny_LeViT_Hardware_Accelerator are comparing it to the libraries listed below
- tpu-systolic-array-weight-stationary☆24Updated 3 years ago
- Accelerate multihead attention transformer model using HLS for FPGA☆11Updated last year
- Open-source of MSD framework☆16Updated last year
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆20Updated 2 years ago
- An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017☆15Updated 5 years ago
- C++ code for HLS FPGA implementation of transformer☆16Updated 7 months ago
- ☆12Updated last year
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆11Updated 4 years ago
- Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator☆27Updated last year
- eyeriss-chisel3☆40Updated 2 years ago
- ☆15Updated 10 months ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆28Updated 3 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆39Updated 6 months ago
- A systolic array matrix multiplier☆24Updated 5 years ago
- CNN accelerator using NoC architecture☆16Updated 6 years ago
- Template for project1 TPU☆18Updated 3 years ago
- ☆14Updated last year
- TinyVers Heterogeneous SoC consists of a reconfigurable FlexML accelerator, a RISC-V processor, an eMRAM and a power management system.☆17Updated last year
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆50Updated 3 months ago
- ☆10Updated 3 years ago
- ☆31Updated 5 years ago
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆40Updated last year
- 关于移植模型至gemmini的文档☆24Updated 2 years ago
- An efficient spatial accelerator enabling hybrid sparse attention mechanisms for long sequences☆26Updated last year
- (Verilog) A simple convolution layer implementation with systolic array structure☆12Updated 2 years ago
- Vision Transformer Accelerator implemented in Vivado HLS for Xilinx FPGAs.☆11Updated 3 months ago
- ☆16Updated 11 months ago
- A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs.☆18Updated last week
- ☆41Updated 4 months ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆30Updated 4 years ago