BoChen-Ye / Tiny_LeViT_Hardware_AcceleratorLinks
This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.
☆23Updated last year
Alternatives and similar repositories for Tiny_LeViT_Hardware_Accelerator
Users that are interested in Tiny_LeViT_Hardware_Accelerator are comparing it to the libraries listed below
Sorting:
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017☆19Updated 6 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Updated 4 years ago
- eyeriss-chisel3☆41Updated 3 years ago
- Template for project1 TPU☆19Updated 4 years ago
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆10Updated 2 years ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆13Updated 4 years ago
- A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs.☆26Updated last month
- Open-source of MSD framework☆16Updated 2 years ago
- Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator☆31Updated last year
- This project is to design yolo AI accelerator in verilog HDL.☆28Updated 11 months ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆59Updated last year
- A scalable Eyeriss model in SystemC.☆29Updated 2 years ago
- C++ code for HLS FPGA implementation of transformer☆18Updated last year
- A systolic array matrix multiplier☆25Updated 6 years ago
- ☆14Updated 2 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆42Updated 2 years ago
- ☆36Updated 6 years ago
- This is a series of quick start guide of Vitis HLS tool in Chinese. It explains the basic concepts and the most important optimize techni…☆23Updated 2 years ago
- ☆17Updated 4 months ago
- CNN accelerator using NoC architecture☆16Updated 6 years ago
- ☆49Updated 5 months ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆13Updated 2 years ago
- Accelerate multihead attention transformer model using HLS for FPGA☆12Updated last year
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆51Updated last year
- ☆68Updated 6 years ago
- Hardware accelerator for convolutional neural networks☆57Updated 3 years ago
- A small Neural Network Processor for Edge devices.☆13Updated 2 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆21Updated 2 years ago
- ☆34Updated 4 months ago