BoChen-Ye / Tiny_LeViT_Hardware_AcceleratorView external linksLinks
This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.
☆32Aug 13, 2024Updated last year
Alternatives and similar repositories for Tiny_LeViT_Hardware_Accelerator
Users that are interested in Tiny_LeViT_Hardware_Accelerator are comparing it to the libraries listed below
Sorting:
- [HPCA'21] SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning☆122Aug 27, 2024Updated last year
- （Not actively updating）Vision Transformer Accelerator implemented in Vivado HLS for Xilinx FPGAs.☆20Dec 29, 2024Updated last year
- ☆63Apr 22, 2025Updated 9 months ago
- You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size o…☆229Mar 24, 2024Updated last year
- OpenExSys_NoC a mesh-based network on chip IP.☆20Dec 1, 2023Updated 2 years ago
- FPGA based Vision Transformer accelerator (Harvard CS205)☆149Feb 11, 2025Updated last year
- verilog实现TPU中的脉动阵列计算卷积的module☆159May 10, 2025Updated 9 months ago
- This repository contains the hardware implementation for Static BFP convolution on FPGA☆10Oct 15, 2019Updated 6 years ago
- a student trainning project for HLS and transformer☆11Oct 19, 2022Updated 3 years ago
- An efficient spatial accelerator enabling hybrid sparse attention mechanisms for long sequences☆31Mar 7, 2024Updated last year
- Model LLM inference on single-core dataflow accelerators☆18Dec 16, 2025Updated last month
- ☆10Oct 8, 2021Updated 4 years ago
- Matrix multiplication accelerator on ZYNQ SoC.☆12Apr 29, 2025Updated 9 months ago
- a hardware task scheduler design☆10Sep 14, 2022Updated 3 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆82Nov 26, 2025Updated 2 months ago
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆12Aug 26, 2023Updated 2 years ago
- ZYNQ-7000 based data transfer through TCP/IP protocol☆12Apr 20, 2023Updated 2 years ago
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆56Nov 22, 2023Updated 2 years ago
- A cycle-accurate RISC-V CPU simulator + RTL modeling library in pure Python.☆18Aug 27, 2025Updated 5 months ago
- R2MDC FFT/IFFT processor adaptive to 64/128/256/512 point☆16Dec 23, 2025Updated last month
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆125Jan 20, 2025Updated last year
- A small Neural Network Processor for Edge devices.☆15Nov 22, 2022Updated 3 years ago
- CPU Design Based on RISCV ISA☆129Jun 14, 2024Updated last year
- RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction…☆25Mar 13, 2025Updated 11 months ago
- Eyeriss‑V1 CNN Hardware Accelerator (Verilog) fully parametric. This repository contains the complete Verilog implementation of a functio…☆24Apr 7, 2025Updated 10 months ago
- This repository presents the source code for the paper "MILLION: Mastering Long-Context LLM Inference Via Outlier-Immunized KV Product Qu…☆23Apr 2, 2025Updated 10 months ago
- A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration☆36May 19, 2022Updated 3 years ago
- 基于FPGA的FFT☆19Feb 18, 2019Updated 6 years ago
- Tender: Accelerating Large Language Models via Tensor Decompostion and Runtime Requantization (ISCA'24)☆25Jul 4, 2024Updated last year
- STONNE Simulator integrated into SST Simulator☆22Apr 5, 2024Updated last year
- [HPCA 2023] ViTCoD: Vision Transformer Acceleration via Dedicated Algorithm and Accelerator Co-Design☆127Jun 27, 2023Updated 2 years ago
- C++ code for HLS FPGA implementation of transformer☆20Sep 11, 2024Updated last year
- An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017☆22May 20, 2019Updated 6 years ago
- [ICTA'21] First Prize Winner of the 2021 DIGILENT Cup, China College Integrated Circuit Competition☆267Apr 1, 2024Updated last year
- The official NaplesPU hardware code repository☆22Jul 27, 2019Updated 6 years ago
- 一个单发射五级静态流水CPU，采用龙芯32位精简版指令集，支持异常和中断处理，使用AXI总线接口，已集成TLB模块☆16Jan 12, 2023Updated 3 years ago
- Methodology that leverages FPV to automatically discover covert channels in hardware that is time-shared between processes. AutoCC operat…☆22Oct 25, 2024Updated last year
- MICRO22 artifact evaluation for Sparseloop☆47Aug 8, 2022Updated 3 years ago
- Theia: ray graphic processing unit☆20Jul 17, 2014Updated 11 years ago