Alternatives and similar repositories for Tiny_LeViT_Hardware_Accelerator

Users that are interested in Tiny_LeViT_Hardware_Accelerator are comparing it to the libraries listed below

• VincentWang1998 / ai_on_chip_project1
  tpu-systolic-array-weight-stationary
  ☆24Updated 4 years ago
• hazooree / LeNet-CNN-Accelerator-Hardware-for-FPGA
  An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017
  ☆18Updated 6 years ago
• AIC2021 / AIC2021_TPU_Template
  Template for project1 TPU
  ☆19Updated 4 years ago
• linkuri267 / cnn_accelerator
  CNN accelerator using NoC architecture
  ☆16Updated 6 years ago
• stellagarden / EE405-Advanced-Digital-Systems-Design
  Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator
  ☆10Updated last year
• CASR-HKU / MSD-FCCM23
  Open-source of MSD framework
  ☆16Updated last year
• KyleParkJong / Network-on-Chip-Simulator
  Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator
  ☆30Updated last year
• lllibano / SystolicArray
  A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs.
  ☆25Updated 3 months ago
• Starrynightzyq / soNN
  A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.
  ☆29Updated 4 years ago
• 8krisv / CNN-ACCELERATOR
  Hardware accelerator for convolutional neural networks
  ☆47Updated 2 years ago
• Spiritator / FPGA_LeNet5_ws_8x8
  FPGA implement of 8x8 weight stationary systolic array DNN accelerator
  ☆12Updated 4 years ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆41Updated 3 years ago
• alexmr09 / Mixed-precision-Neural-Networks-on-RISC-V-Cores
  ☆31Updated 2 months ago
• jha-lab / codebench
  [TECS'23] A project on the co-design of Accelerators and CNNs.
  ☆20Updated 2 years ago
• wzc810049078 / systolic-array-matrix-multiplier
  A systolic array matrix multiplier
  ☆24Updated 5 years ago
• HanPU-Code / CNN_YOLO_AI_accelerator
  This project is to design yolo AI accelerator in verilog HDL.
  ☆19Updated 9 months ago
• pulp-platform / ITA
  ☆47Updated 3 months ago
• kuladeepsaireddy / OpenNoc
  ☆34Updated 6 years ago
• bsc-loca / sauria
  SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…
  ☆51Updated 10 months ago
• ac-optimus / Convolution-using-systolic-arrays
  ☆65Updated 6 years ago
• evan199893 / TPU_systolic_array_HW_accelerator
  Tensor Processing Unit implementation in Verilog
  ☆8Updated 4 months ago
• gem5-X / TiC-SAT
  ☆17Updated 2 months ago
• adervay1 / CIMulator
  a Computing In Memory emULATOR framework
  ☆13Updated last year
• CASR-HKU / AGNA-FCCM2023
  ☆12Updated last year
• avikram2 / RISCVPipelinedProcessor
  Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…
  ☆13Updated 2 years ago
• sjj-star / automatically-generate-Wallace-Tree-VerilogHDL-code
  本工具用于自动生成一个Wallace Tree算法VerilogHDL代码实例，并附带了一些配套的工具和一个完整的VerilogHDL描述的乘法器。
  ☆25Updated 2 years ago
• yuehniu / CNN.frequencyFPGA
  CNN Accelerator in Frequency Domain
  ☆12Updated 5 years ago
• gl9544 / vit_transformer_fpga
  ☆15Updated last year
• vickyiii / Quick-Start-Guide-for-HLS
  This is a series of quick start guide of Vitis HLS tool in Chinese. It explains the basic concepts and the most important optimize techni…
  ☆22Updated 2 years ago
• puccinic / Transformer_dataflow
  C++ code for HLS FPGA implementation of transformer
  ☆17Updated 10 months ago