Alternatives and similar repositories for slang-lsp-tools

Users that are interested in slang-lsp-tools are comparing it to the libraries listed below

• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆58Updated 3 months ago
• Kuree / hgdb
  Hardware generator debugger
  ☆73Updated last year
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆39Updated 2 years ago
• alainmarcel / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Li…
  ☆26Updated 3 weeks ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆56Updated 6 months ago
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆30Updated last week
• ThePerfectComputer / FastWaveBackend
  A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.
  ☆44Updated 4 months ago
• antmicro / verilator-verification-features-tests
  ☆20Updated this week
• nanamake / vcd2json
  Create WaveJSON from VCD file. WaveDrom can convert it to timing diagram.
  ☆38Updated 9 months ago
• Nic30 / pyDigitalWaveTools
  Python library for operations with VCD and other digital wave files
  ☆49Updated 11 months ago
• Ben1152000 / sootty
  A command-line tool for displaying vcd waveforms.
  ☆56Updated last year
• vivekmalneedi / veridian
  A SystemVerilog Language Server
  ☆168Updated last month
• fvutils / pyhdl-if
  Python interface for cross-calling with HDL
  ☆32Updated 2 months ago
• chipsalliance / UHDM-integration-tests
  ☆31Updated last year
• antmicro / sv-bugpoint
  ☆26Updated 3 weeks ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆103Updated this week
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆29Updated 10 months ago
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆64Updated last week
• benbr8 / rstb
  Rust Test Bench - write HDL tests in Rust.
  ☆23Updated 2 years ago
• antoinemadec / uvm_code_gen
  Simple template-based UVM code generator
  ☆26Updated 2 years ago
• raczben / fliplot
  HTML & Js based VCD viewer
  ☆60Updated 4 years ago
• Intuity / forastero
  Making cocotb testbenches that bit easier
  ☆29Updated last month
• sgherbst / svinst
  Determines the modules declared and instantiated in a SystemVerilog file
  ☆44Updated 7 months ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆65Updated 8 months ago
• chipsalliance / espresso
  ☆39Updated last year
• imc-trading / svlangserver
  ☆109Updated 11 months ago
• umarcor / osvb
  Open Source Verification Bundle for VHDL and System Verilog
  ☆45Updated last year
• dh73 / A_Formal_Tale_Chapter_I_AMBA
  AXI Formal Verification IP
  ☆20Updated 4 years ago
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆51Updated 2 weeks ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆76Updated 2 years ago