Tools based upon slang for language server purpose
☆24Sep 10, 2026Updated last month
Alternatives and similar repositories for slang-lsp-tools
Users that are interested in slang-lsp-tools are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A SystemVerilog language server based on the Slang library.☆352Updated this week
- SystemVerilog design elaborator into word-level netlist form☆255Updated this week
- A tool for analysing the source-level static connectivity of a SystemVerilog design☆29Oct 7, 2026Updated last month
- SystemVerilog Linter based on pyslang☆34May 5, 2025Updated last year
- SystemVerilog compiler and language services☆1,177Updated this week
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆40Updated this week
- ☆21Mar 3, 2026Updated 8 months ago
- ☆16Aug 11, 2026Updated 2 months ago
- ☆10Sep 8, 2023Updated 3 years ago
- ☆13Feb 13, 2021Updated 5 years ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆478Updated this week
- Test dashboard for verification features in Verilator☆36Updated this week
- Implementation of Tagged Memory security policies into Rocket Core☆10Nov 8, 2016Updated 9 years ago
- ☆102Jul 22, 2026Updated 3 months ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- Hardware generator debugger☆79Feb 12, 2024Updated 2 years ago
- Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.☆90Mar 28, 2026Updated 7 months ago
- Consistency checker for memory subsystem traces☆22Oct 10, 2016Updated 10 years ago
- ☆43May 26, 2018Updated 8 years ago
- A dependency management tool for hardware projects.☆401Oct 22, 2026Updated 2 weeks ago
- ☆12May 20, 2021Updated 5 years ago
- Fiber-based SystemVerilog Simulator.☆25Jul 29, 2022Updated 4 years ago
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆41Jan 16, 2025Updated last year
- ☆32Jan 7, 2025Updated last year
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Equivalence checking with Yosys☆68Oct 27, 2026Updated last week
- FPGA config visualized. demo:☆20Mar 17, 2020Updated 6 years ago
- Native Rust implementation of the FST waveform format from GTKWave.☆15Oct 13, 2026Updated 3 weeks ago
- cpp parser for reading a VCD (value change dump) file☆10Jul 15, 2013Updated 13 years ago
- BFM Tester for Chisel HDL☆14Nov 27, 2021Updated 4 years ago
- Documenting the Xilinx 7-series bit-stream format.☆16Updated this week
- command line tool for frequent amaranth HDL tasks (generate sources, show design)☆17Dec 27, 2021Updated 4 years ago
- A simple template for simple FPGA projects (mostly Verilog HDL and Xilinx Toolchain)☆10May 2, 2014Updated 12 years ago
- Lightweight re-packaging of AsyncQueue library from rocket-chip☆18Jun 23, 2023Updated 3 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Nix flake for more up-to-date versions of EDA tools☆35Updated this week
- Hardware Formal Verification Tool☆125Updated this week
- ☆17Jul 12, 2024Updated 2 years ago
- Verilator open-source SystemVerilog simulator and lint system☆29Updated this week
- Tcl package that provides access to a Python interpreter☆16Sep 1, 2022Updated 4 years ago
- The SiFive wake build tool☆95Updated this week
- The 'missing header' for Chisel☆24Feb 5, 2026Updated 9 months ago