Tools based upon slang for language server purpose
☆21Feb 4, 2026Updated last month
Alternatives and similar repositories for slang-lsp-tools
Users that are interested in slang-lsp-tools are comparing it to the libraries listed below
Sorting:
- Implementation of Tagged Memory security policies into Rocket Core☆10Nov 8, 2016Updated 9 years ago
- ☆13Feb 13, 2021Updated 5 years ago
- ☆12May 20, 2021Updated 4 years ago
- BFM Tester for Chisel HDL☆14Nov 27, 2021Updated 4 years ago
- command line tool for frequent amaranth HDL tasks (generate sources, show design)☆17Dec 27, 2021Updated 4 years ago
- FPGA config visualized. demo:☆20Mar 17, 2020Updated 5 years ago
- ☆20Updated this week
- Consistency checker for memory subsystem traces☆23Oct 10, 2016Updated 9 years ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆28Nov 21, 2019Updated 6 years ago
- ☆20Feb 9, 2020Updated 6 years ago
- firrtlator is a FIRRTL C++ library☆23Dec 15, 2016Updated 9 years ago
- Rust Test Bench - write HDL tests in Rust.☆24Nov 28, 2022Updated 3 years ago
- The home of the Chisel3 website☆21May 24, 2024Updated last year
- Test dashboard for verification features in Verilator☆31Updated this week
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆36Jan 26, 2026Updated last month
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆36Jan 16, 2025Updated last year
- SystemVerilog Linter based on pyslang☆31May 5, 2025Updated 10 months ago
- Simple template-based UVM code generator☆29Jan 4, 2023Updated 3 years ago
- BSC Development Workstation (BDW)☆32Feb 16, 2026Updated 3 weeks ago
- Semi-private RTL development upstream of OpenCPI - this is *not* the OpenCPI repo!☆25Oct 19, 2016Updated 9 years ago
- Chisel artifacts developed under IBM's involvement with the DARPA PERFECT program☆30Sep 17, 2025Updated 5 months ago
- Hardware generator debugger☆77Feb 12, 2024Updated 2 years ago
- A dependency management tool for hardware projects.☆349Mar 3, 2026Updated last week
- MATLAB/Octave generator of Hamming ECC coding. Output format is Verilog HDL.☆12Dec 27, 2022Updated 3 years ago
- ☆42Jan 23, 2026Updated last month
- ☆91Oct 13, 2025Updated 4 months ago
- sram/rram/mram.. compiler☆47Sep 11, 2023Updated 2 years ago
- Virtual development board for HDL design☆42Mar 31, 2023Updated 2 years ago
- SystemVerilog frontend for Yosys☆203Feb 22, 2026Updated 2 weeks ago
- build and package Inkscape on macOS☆10Dec 11, 2025Updated 2 months ago
- Torc: Tools for Open Reconfigurable Computing☆39Apr 12, 2017Updated 8 years ago
- The SiFive wake build tool☆92Updated this week
- SystemVerilog compiler and language services☆968Mar 3, 2026Updated last week
- 🔍 Zoomable Waveform viewer for the Web☆43Nov 3, 2020Updated 5 years ago
- A hand-written recursive decent Verilog parser.☆10Jan 30, 2026Updated last month
- A stream to RTL compiler based on MLIR and CIRCT☆16Nov 15, 2022Updated 3 years ago
- ☆15Dec 9, 2025Updated 3 months ago
- VHDL ieee_proposed library, imported as is. See also https://github.com/FPHDL/fphdl☆12Aug 26, 2016Updated 9 years ago
- cpp parser for reading a VCD (value change dump) file☆10Jul 15, 2013Updated 12 years ago