Alternatives and similar repositories for slang-lsp-tools

Users that are interested in slang-lsp-tools are comparing it to the libraries listed below

• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆60Updated 6 months ago
• suoto / hdl_checker
  Repurposing existing HDL tools to help writing better code
  ☆215Updated last year
• Kuree / hgdb
  Hardware generator debugger
  ☆74Updated last year
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆70Updated last week
• nanamake / vcd2json
  Create WaveJSON from VCD file. WaveDrom can convert it to timing diagram.
  ☆39Updated last year
• raczben / fliplot
  HTML & Js based VCD viewer
  ☆61Updated last week
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆54Updated last month
• vivekmalneedi / veridian
  A SystemVerilog Language Server
  ☆177Updated 3 months ago
• avelure / doxygen-verilog
  Doxygen with verilog support
  ☆38Updated 6 years ago
• sgherbst / svinst
  Determines the modules declared and instantiated in a SystemVerilog file
  ☆47Updated 10 months ago
• Nic30 / pyDigitalWaveTools
  Python library for operations with VCD and other digital wave files
  ☆51Updated last month
• tree-sitter / tree-sitter-verilog
  SystemVerilog grammar for tree-sitter
  ☆104Updated 8 months ago
• Ben1152000 / sootty
  A command-line tool for displaying vcd waveforms.
  ☆59Updated last year
• umarcor / osvb
  Open Source Verification Bundle for VHDL and System Verilog
  ☆45Updated last year
• imc-trading / svlangserver
  ☆115Updated last year
• antmicro / verilator-verification-features-tests
  ☆27Updated this week
• fvutils / pyhdl-if
  Python interface for cross-calling with HDL
  ☆34Updated last month
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆123Updated this week
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆31Updated 2 months ago
• Intuity / forastero
  Making cocotb testbenches that bit easier
  ☆34Updated last week
• alainmarcel / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Li…
  ☆26Updated this week
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆59Updated 9 months ago
• kevinpt / hdlparse
  Simple parser for extracting VHDL documentation
  ☆71Updated last year
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆41Updated 2 years ago
• rameloni / tywaves-chisel
  A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…
  ☆46Updated 8 months ago
• mciepluc / cocotb-coverage
  Functional Coverage and Constrained Randomization Extensions for Cocotb
  ☆114Updated last year
• agra-uni-bremen / crave
  Constrained random stimuli generation for C++ and SystemC
  ☆52Updated last year
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆222Updated this week
• dpretet / svut
  SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
  ☆80Updated 9 months ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆143Updated this week