suzizecat / slang-lsp-toolsLinks
Tools based upon slang for language server purpose
☆15Updated this week
Alternatives and similar repositories for slang-lsp-tools
Users that are interested in slang-lsp-tools are comparing it to the libraries listed below
Sorting:
- Python bindings for slang, a library for compiling SystemVerilog☆59Updated 5 months ago
- Hardware generator debugger☆74Updated last year
- A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.☆44Updated 6 months ago
- A command-line tool for displaying vcd waveforms.☆59Updated last year
- SystemVerilog Linter based on pyslang☆31Updated last month
- ☆24Updated this week
- Python interface for cross-calling with HDL☆33Updated 3 weeks ago
- Making cocotb testbenches that bit easier☆33Updated this week
- ☆112Updated last year
- YosysHQ SVA AXI Properties☆40Updated 2 years ago
- Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.☆67Updated last week
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Li…☆26Updated this week
- A SystemVerilog Language Server☆175Updated 2 months ago
- A SystemVerilog source file pickler.☆57Updated 8 months ago
- Repurposing existing HDL tools to help writing better code☆210Updated last year
- Python script to transform a VCD file to wavedrom format☆77Updated 2 years ago
- SystemVerilog grammar for tree-sitter☆100Updated 7 months ago
- Simple parser for extracting VHDL documentation☆71Updated 11 months ago
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆55Updated this week
- Limited python / cocotb interface to Xilinx/AMD Vivado simulator.☆44Updated 5 months ago
- A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.☆97Updated 3 years ago
- Generate address space documentation HTML from compiled SystemRDL input☆54Updated last week
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆17Updated this week
- Python packages providing a library for Verification Stimulus and Coverage☆123Updated last month
- Doxygen with verilog support☆37Updated 6 years ago
- Python library for operations with VCD and other digital wave files☆51Updated 2 weeks ago
- A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…☆46Updated 8 months ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated 11 months ago
- Re-coded Xilinx primitives for Verilator use☆49Updated this week
- ☆26Updated last week