thesourcerer8 / StdCellLibLinks
LibreSilicon's Standard Cell Library Generator
☆20Updated last year
Alternatives and similar repositories for StdCellLib
Users that are interested in StdCellLib are comparing it to the libraries listed below
Sorting:
- An open source PDK using TIGFET 10nm devices.☆49Updated 2 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- ☆20Updated 3 years ago
- An SRAM IP Uniquely designed with open source tools. Static RAM is a type of random-access memory that uses latching circuitry (flip-flop…☆11Updated 5 years ago
- Minimal SKY130 example with self-checking LVS, DRC, and PEX☆23Updated 4 years ago
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆31Updated 4 years ago
- Analog and power building blocks for sky130 pdk☆20Updated 4 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆42Updated 2 years ago
- ☆38Updated 3 years ago
- ☆44Updated 5 years ago
- Design of 4KB(1024*32) SRAM with operating voltage 1.8v and access time < 2.5ns☆13Updated 4 years ago
- Open source process design kit for 28nm open process☆60Updated last year
- ☆17Updated 9 months ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆23Updated last month
- https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/☆28Updated 6 months ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 5 years ago
- ☆18Updated 9 months ago
- submission repository for efabless mpw6 shuttle☆30Updated last year
- Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM☆19Updated 4 years ago
- SRAM☆22Updated 4 years ago
- ☆55Updated last year
- Design of 4KB Static RAM 1.8V (access time <2.5ns) using OpenRAM and Sky130 node☆13Updated 4 years ago
- A repository for Known Good Designs (KGDs). Does not contain any design files with NDA-sensitive information.☆36Updated 4 years ago
- A current mode buck converter on the SKY130 PDK☆27Updated 4 years ago
- Open Analog Design Environment☆24Updated 2 years ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆37Updated last month
- A configurable SRAM generator☆53Updated 3 weeks ago
- Design of Analog Blocks in Skywaters 130nm meeting corners: different flavors of OTA, BandGap, LDO.☆27Updated 3 years ago
- tools regarding on analog modeling, validation, and generation☆22Updated 2 years ago