thesourcerer8 / StdCellLibLinks
LibreSilicon's Standard Cell Library Generator
☆22Updated 2 months ago
Alternatives and similar repositories for StdCellLib
Users that are interested in StdCellLib are comparing it to the libraries listed below
Sorting:
- An open source PDK using TIGFET 10nm devices.☆54Updated 3 years ago
- An SRAM IP Uniquely designed with open source tools. Static RAM is a type of random-access memory that uses latching circuitry (flip-flop…☆13Updated 5 years ago
- ☆20Updated 4 years ago
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆33Updated 3 weeks ago
- ☆44Updated 5 years ago
- Design of 4KB(1024*32) SRAM with operating voltage 1.8v and access time < 2.5ns☆14Updated 5 years ago
- ☆19Updated last year
- A repository for Known Good Designs (KGDs). Does not contain any design files with NDA-sensitive information.☆39Updated 4 years ago
- ☆38Updated 3 years ago
- Open Analog Design Environment☆25Updated 2 years ago
- ☆17Updated last year
- submission repository for efabless mpw6 shuttle☆31Updated 2 years ago
- Completed LDO Design for Skywaters 130nm☆18Updated 2 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆44Updated 2 years ago
- Analog and power building blocks for sky130 pdk☆22Updated 4 years ago
- https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/☆28Updated 11 months ago
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆38Updated 4 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- Gate-level visualization generator for SKY130-based chip designs.☆21Updated 4 years ago
- tools regarding on analog modeling, validation, and generation☆22Updated 2 years ago
- Minimal SKY130 example with self-checking LVS, DRC, and PEX☆24Updated 4 years ago
- AHB-Lite based SoC for IBEX/SWERV/VEXRISC/...☆13Updated 9 months ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 3 years ago
- Skywater 130nm Klayout Device Generators PDK☆30Updated last year
- Wavious DDR (WDDR) Physical interface (PHY) Software☆22Updated 3 years ago
- Open Source PHY v2☆33Updated last year
- Design of Analog Blocks in Skywaters 130nm meeting corners: different flavors of OTA, BandGap, LDO.☆29Updated 3 years ago
- Source codes and calibration scripts for clock tree synthesis☆40Updated 5 years ago
- Extended and external tests for Verilator testing☆17Updated 2 weeks ago
- Library of open source Process Design Kits (PDKs)☆64Updated this week