ic-lab-duth / Fast-Float4HLS
Fast Floating Point Operators for High Level Synthesis
☆20Updated last year
Alternatives and similar repositories for Fast-Float4HLS:
Users that are interested in Fast-Float4HLS are comparing it to the libraries listed below
- Wraps the NVDLA project for Chipyard integration☆19Updated 10 months ago
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Updated 7 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆19Updated 2 years ago
- ☆24Updated 5 years ago
- ☆3Updated 3 years ago
- Algorithmic C Machine Learning Library☆22Updated last month
- Stencil with Optimized Dataflow Architecture☆12Updated 10 months ago
- Systolic Three Matrix Multiplier for Graph Convolutional Networks using High Level Synthesis☆22Updated 2 years ago
- SForum 2020 : "A Run-time Hardware Routing Implementation for CGRA Overlays" code and data.☆11Updated 4 years ago
- A static dataflow CGRA with dynamic dataflow execution capability☆10Updated 3 years ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆21Updated 3 years ago
- Reconfigurable Binary Engine☆15Updated 3 years ago
- This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times …☆22Updated 5 years ago
- DUTH RISC V Microprocessor for High Level Synthesis☆10Updated last year
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 4 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆40Updated 4 years ago
- FPGA acceleration of arbitrary precision floating point computations.☆38Updated 2 years ago
- Domain-Specific Architecture Generator 2☆21Updated 2 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆48Updated 7 years ago
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated 4 months ago
- HLS project modeling various sparse accelerators.☆12Updated 3 years ago
- HLS for Networks-on-Chip☆32Updated 3 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 2 years ago
- Express DLA implementation for FPGA, revised based on NVDLA.☆9Updated 5 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆26Updated 3 months ago
- Provides the code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators" by Luk…☆17Updated 5 years ago
- cycle accurate Network-on-Chip Simulator☆25Updated last year
- Verilog behavioral description of various memories☆30Updated 2 years ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆25Updated this week
- RISC-V ISA based 32-bit processor written in HLS☆17Updated 5 years ago